公开(公告)号：US11710772B2

公开(公告)日：2023-07-25

申请号：US17560865

申请日：2021-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunhye Choi ,  Seung Mo Kang ,  Jungtaek Kim ,  Moon Seung Yang ,  Jongryeol Yoo

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/105 ,  H01L29/0852 ,  H01L29/1079 ,  H01L29/42356 ,  H01L29/66712 ,  H01L29/7802

Abstract: A semiconductor device including an insulating layer on a substrate; channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other; a gate electrode crossing the channel semiconductor patterns; source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces; and air gaps between the insulating layer and the bottom surfaces of the source/drain regions.

公开(公告)号：US09991257B2

公开(公告)日：2018-06-05

申请号：US15013969

申请日：2016-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miseon Park ,  Jongryeol Yoo ,  Hyunjung Lee ,  Yong-Suk Tak ,  Bonyoung Koo ,  Sunjung Kim

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/161 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41791

Abstract: A semiconductor device may include fin active regions extending parallel to each other on a substrate, an isolation region between the fin active regions, gate patterns intersecting the fin active regions and extending parallel to each other, source/drain areas on the fin active regions between the gate patterns and fin active region spacers contacting side surfaces of the fin active regions and formed over a surface of the isolation region between the fin active regions. Uppermost levels of the fin active region spacers may be higher than interfaces between the fin active regions and the source/drain areas. The upper surface of the isolation region may be lower than bottom surfaces of the source/drain areas.

公开(公告)号：US20250006830A1

公开(公告)日：2025-01-02

申请号：US18591569

申请日：2024-02-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryeol Yoo

IPC: H01L29/775 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes an insulating substrate, a silicon layer on the insulating substrate, a dopant layer on the silicon layer, a buried spacer on a side surface of the dopant layer, a channel pattern on the dopant layer, the channel pattern comprising a plurality of semiconductor patterns vertically stacked and spaced apart from each other, a source/drain pattern on the buried spacer, the source/drain pattern connected to the channel pattern, a gate electrode on the channel pattern, the gate electrode comprising a plurality of inner electrodes between the semiconductor patterns, respectively, a lower power interconnection line in a lower portion of the insulating substrate, and a backside contact extending into the insulating substrate and the silicon layer to electrically connect the lower power interconnection line to the source/drain pattern. A side surface of the backside contact is in contact with the silicon layer and the buried spacer.

公开(公告)号：US11688813B2

公开(公告)日：2023-06-27

申请号：US17584545

申请日：2022-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Mo Kang ,  Moon Seung Yang ,  Jongryeol Yoo ,  Sihyung Lee ,  Sunguk Jang ,  Eunhye Choi

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L29/78696 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02664 ,  H01L21/311 ,  H01L21/3247 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/785 ,  H01L29/7848

Abstract: A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.

公开(公告)号：US09728644B2

公开(公告)日：2017-08-08

申请号：US15093892

申请日：2016-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Suk Tak ,  Jongryeol Yoo ,  Hyun Jung Lee ,  Miseon Park ,  Bonyoung Koo ,  Sunjung Kim

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7849

Abstract: A semiconductor device includes a fin structure on a substrate and extending in a first direction, a gate electrode crossing over the fin structure, source/drain regions on the fin structure at opposite sides of the gate electrode, and a barrier layer between the fin structure and each of the source/drain regions. The fin structure includes a material having a lattice constant different from that of the substrate, the fin structure, the source/drain regions, and the barrier layer include germanium, and a germanium concentration in the barrier layer is greater than that in the fin structure and less than a maximum germanium concentration in each of the source/drain regions.

公开(公告)号：US20240363701A1

公开(公告)日：2024-10-31

申请号：US18492327

申请日：2023-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongryeol Yoo

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present disclosure relates to semiconductor devices and their fabrication methods. One example semiconductor device comprises a substrate that includes an active region, an active pattern on the active region, a source/drain pattern on the active pattern, an active contact that extends from a top surface to a sidewall of the source/drain pattern and includes a first part that covers the sidewall of the source/drain pattern and a second part that covers the top surface of the source/drain pattern, a first layer between the source/drain pattern and the first part, and a second layer separated from the first layer and across the first part. Each of the first layer and the second layer includes a silicide layer.

公开(公告)号：US11616144B2

公开(公告)日：2023-03-28

申请号：US16412796

申请日：2019-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunguk Jang ,  Sujin Jung ,  Jinyeong Joe ,  Jeongho Yoo ,  Seung Hun Lee ,  Jongryeol Yoo

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/417 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor device includes a first active fin protruding from a substrate, a first gate pattern covering a side surface and a top surface of the first active fin, and first source/drain patterns at opposite sides of the first gate pattern, each of the first source/drain patterns including a first lower side and a second lower side spaced apart from each other, a first upper side extended from the first lower side, a second upper side extended from the second lower side. The first lower side may be inclined at a first angle relative to a top surface of the substrate, the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.

公开(公告)号：US20190252526A1

公开(公告)日：2019-08-15

申请号：US16116577

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryeol Yoo ,  Jeongho Yoo ,  Sujin Jung ,  Youngdae Cho

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8238

Abstract: A semiconductor device includes a well region in a substrate, a semiconductor pattern on the well region, the semiconductor pattern including an impurity, and a gate electrode on the semiconductor pattern. A concentration of the impurity in the semiconductor pattern increases in a direction from an upper portion of the semiconductor pattern, adjacent to the gate electrode, to a lower portion of the semiconductor pattern, adjacent to the well region.

公开(公告)号：US09508832B2

公开(公告)日：2016-11-29

申请号：US14749037

申请日：2015-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Jung Lee ,  Bonyoung Koo ,  Sunjung Kim ,  Jongryeol Yoo ,  Seung Hun Lee ,  Poren Tang

IPC: H01L21/306 ,  H01L21/308 ,  H01L21/336 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/3085 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823807

Abstract: A method of fabricating a semiconductor device includes forming a channel layer on a substrate, forming a sacrificial layer on the channel layer, forming a hardmask pattern on the sacrificial layer, and performing a patterning process using the hardmask pattern as an etch mask to form a channel portion with an exposed top surface. The channel and sacrificial layers may be formed of silicon germanium, and the sacrificial layer may have a germanium content higher than that of the channel layer.

Abstract translation: 制造半导体器件的方法包括在衬底上形成沟道层，在沟道层上形成牺牲层，在牺牲层上形成硬掩模图案，并使用硬掩模图案作为蚀刻掩模进行图案化处理，形成 通道部分具有​​暴露的顶表面。 通道和牺牲层可由硅锗形成，并且牺牲层的锗含量可高于沟道层的锗含量。

公开(公告)号：US20240128321A1

公开(公告)日：2024-04-18

申请号：US18378874

申请日：2023-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongryeol Yoo ,  Jungtaek Kim

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes an active region including a first portion and a second portion; an isolation region on a side surface of the active region; a plurality of active layers stacked and spaced apart from each other in a vertical direction on the first portion of the active region; an epitaxial structure disposed on the second portion of the active region, connected to the plurality of active layers, and overlapping the isolation region in the vertical direction; a gate structure extending by intersecting the active region and surrounding each of the plurality of active layers; and a gate spacer on a side surface of the gate structure. The epitaxial structure includes a blocking layer and a source/drain structure on the blocking layer. The blocking layer includes a plurality of active blocking portions contacting the plurality of active layers, respectively, and at least one first bent portion bent and extending from at least one of the plurality of active blocking portions and contacting the gate spacer.