公开(公告)号：US10950612B2

公开(公告)日：2021-03-16

申请号：US15981928

申请日：2018-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggil Kim ,  Sangsoo Lee ,  Seulye Kim ,  Hongsuk Kim ,  Jintae Noh ,  Ji-Hoon Choi ,  Jaeyoung Ahn ,  Sanghoon Lee

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/78 ,  G11C16/04 ,  H01L29/66 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor memory device has a plurality of gates vertically stacked on a top surface of a substrate, a vertical channel filling a vertical hole that extends vertically through the plurality of gates, and a memory layer in the vertical hole and surrounding the vertical channel. The vertical channel includes a bracket-shaped lower portion filling part of a recess in the top of the substrate and an upper portion extending vertically along the vertical hole and connected to the lower channel. At least one end of an interface between the lower and upper portions of the vertical channel is disposed at a level not than that of the top surface of the substrate.

公开(公告)号：US10109747B2

公开(公告)日：2018-10-23

申请号：US14831449

申请日：2015-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byong-Hyun Jang ,  Juhyung Kim ,  Woonkyung Lee ,  Jaegoo Lee ,  Chaeho Kim ,  Junkyu Yang ,  Phil Ouk Nam ,  Jaeyoung Ahn ,  Kihyun Hwang

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L29/04 ,  H01L29/10 ,  H01L23/528 ,  H01L29/51 ,  H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

公开(公告)号：US11282856B2

公开(公告)日：2022-03-22

申请号：US16845615

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Sunggil Kim ,  Seulye Kim ,  HongSuk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/792 ,  H01L29/423 ,  H01L29/04 ,  H01L27/11565 ,  H01L29/51

Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.

公开(公告)号：US10103170B2

公开(公告)日：2018-10-16

申请号：US15784635

申请日：2017-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byong-hyun Jang ,  Dongchul Yoo ,  Woojin Jang ,  Jaeyoung Ahn ,  Junkyu Yang

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  H01L29/51 ,  H01L27/11568 ,  H01L21/311 ,  H01L21/28 ,  H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L27/11565

Abstract: A semiconductor device includes word lines vertically stacked on top of each other on a substrate, insulating patterns between the word lines, a vertical pillar connected to the substrate, and residual sacrificial patterns on the substrate at sides of the word lines. The vertical pillar penetrates the word lines and the insulating patterns. Each of the insulating patterns includes a first portion between the word lines and a second portion extending from the first portion and between the residual sacrificial patterns. A first thickness of the first portion is smaller than a second thickness of the second portion.

公开(公告)号：US08765538B2

公开(公告)日：2014-07-01

申请号：US14061304

申请日：2013-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

IPC: H01L21/336

CPC classification number: H01L29/66666 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

Abstract translation: 提供三维半导体存储器件及其形成方法。 该器件包括衬底，堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案可以包括设置在有源图案的上部的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US10727115B2

公开(公告)日：2020-07-28

申请号：US16460598

申请日：2019-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Phil Ouk Nam ,  Jaeyoung Ahn ,  Sangsoo Lee

IPC: H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11575 ,  G11C16/30 ,  G11C16/08 ,  G11C16/04 ,  H01L27/11565

Abstract: Provided is a semiconductor device including a lower layer structure on a substrate, the lower layer structure having different thicknesses on first and second regions of the substrate, the lower layer structure including an electrode layer at a top and an insulating layer thereunder, an etch stop layer on the lower layer structure, an upper layer structure on the etch stop layer, the etch stop layer having an etch selectivity to the upper and lower layer structures, first and second contact plugs filling first and second openings defined in the upper layer structure and the etch stop layer on the first and second regions, respectively, and contacting corresponding electrode layers of the lower layer structure, respectively, such that one of the first and second contact plugs downwardly extends further with respect to a bottom of the etch stop layer than the other one of the first and second contact plugs.

公开(公告)号：US10396094B2

公开(公告)日：2019-08-27

申请号：US15849121

申请日：2017-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hoon Choi ,  Sunggil Kim ,  Seulye Kim ,  Hongsuk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.

公开(公告)号：US10263006B2

公开(公告)日：2019-04-16

申请号：US15480983

申请日：2017-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gil Kim ,  Ji-Hoon Choi ,  Dongkyum Kim ,  Jintae Noh ,  Seulye Kim ,  Hong Suk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/08 ,  H01L29/10 ,  H01L27/1157 ,  H01L29/423

Abstract: A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.

公开(公告)号：US20140099761A1

公开(公告)日：2014-04-10

申请号：US14061304

申请日：2013-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

IPC: H01L29/66 ,  H01L27/115

CPC classification number: H01L29/66666 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

Abstract translation: 提供三维半导体存储器件及其形成方法。 该器件包括衬底，堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案可以包括设置在有源图案的上部的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US10892278B2

公开(公告)日：2021-01-12

申请号：US16509169

申请日：2019-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hoon Choi ,  Sunggil Kim ,  Seulye Kim ,  Hongsuk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L27/11582 ,  H01L29/06 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11565 ,  H01L29/10 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51

Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.