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    Three-dimensional semiconductor devices and methods of fabricating the same
    1.
    发明授权
    Three-dimensional semiconductor devices and methods of fabricating the same 有权

    公开(公告)号：US11792993B2

    公开(公告)日：2023-10-17

    申请号：US17859631

    申请日：2022-07-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunggil Kim ,  Sungjin Kim ,  Seulye Kim ,  Junghwan Kim ,  Chanhyoung Kim

    IPC: H10B43/27 ,  H01L29/10

    CPC classification number: H10B43/27 ,  H01L29/105 ,  H01L29/1037

    Abstract: A three-dimensional semiconductor device including a conductive layer disposed on a substrate and including a first conductivity-type impurity; an insulating base layer disposed on the conductive layer; a stack structure including a lower insulating film disposed on the insulating base layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating base layer includes a high dielectric material; a vertical structure including a vertical channel layer penetrating through the stack structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extended area extending in a width direction in the insulating base layer; and an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, and extending in a direction parallel to an upper surface of the substrate, wherein the conductive layer has an extension portion extending along a surface of the vertical channel layer in the extended area of the vertical structure.

    Semiconductor device and method of manufacturing the same
    8.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08962444B2

    公开(公告)日：2015-02-24

    申请号：US14053913

    申请日：2013-10-15

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Jung-Hwan Kim ,  Sunggil Kim ,  HongSuk Kim ,  Guk-Hyon Yon ,  Hunhyeong Lim

    IPC: H01L21/76 ,  H01L21/762

    CPC classification number: H01L21/76224 ,  H01L21/28273 ,  H01L21/32155 ,  H01L21/764 ,  H01L27/11524

    Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively.

    Abstract translation: 提供制造半导体器件的方法。 该方法包括在衬底上形成掺杂有第一p型掺杂剂的多晶硅层，蚀刻多晶硅层和衬底以形成多晶硅图案和沟槽，从而形成覆盖层的下侧壁的器件隔离图案 沟槽中的多晶硅图案，在包括第二p型掺杂剂的气体中热处理多晶硅图案，在热处理的多晶硅图案和器件隔离图案上形成电介质层和导电层，蚀刻导电 层，电介质层和热处理的多晶硅图案，以分别形成控制栅极，电介质图案和浮置栅极。

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    9.
    发明公开
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240243183A1

    公开(公告)日：2024-07-18

    申请号：US18462724

    申请日：2023-09-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangmin Kang ,  Sunggil Kim ,  Kyungwook Park

    IPC: H01L29/45 ,  H01L23/00 ,  H01L29/417

    CPC classification number: H01L29/456 ,  H01L24/08 ,  H01L29/41741 ,  H10B43/27

    Abstract: A semiconductor device includes: a first substrate structure including a first substrate, circuit devices, and first bonding pads; and a second substrate structure connected to the first substrate structure. The second substrate structure includes: a source structure; gate electrodes stacked and spaced apart from each other below the source structure in a first direction; first contact plugs electrically connected to the gate electrodes and extending in the first direction; a second contact plug extending in the first direction in an external side of the gate electrodes and electrically connected to the source structure through an upper end; a diffusion barrier between the second contact plug and the source structure, wherein a level of a lower end thereof is higher than a level of an uppermost surface of the gate electrodes; and second bonding pads below the gate electrodes and connected to the first bonding pads.

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