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    Three-dimensional semiconductor devices and methods of fabricating the same
    1.
    发明授权
    Three-dimensional semiconductor devices and methods of fabricating the same 有权

    公开(公告)号：US11792993B2

    公开(公告)日：2023-10-17

    申请号：US17859631

    申请日：2022-07-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunggil Kim ,  Sungjin Kim ,  Seulye Kim ,  Junghwan Kim ,  Chanhyoung Kim

    IPC: H10B43/27 ,  H01L29/10

    CPC classification number: H10B43/27 ,  H01L29/105 ,  H01L29/1037

    Abstract: A three-dimensional semiconductor device including a conductive layer disposed on a substrate and including a first conductivity-type impurity; an insulating base layer disposed on the conductive layer; a stack structure including a lower insulating film disposed on the insulating base layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating base layer includes a high dielectric material; a vertical structure including a vertical channel layer penetrating through the stack structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extended area extending in a width direction in the insulating base layer; and an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, and extending in a direction parallel to an upper surface of the substrate, wherein the conductive layer has an extension portion extending along a surface of the vertical channel layer in the extended area of the vertical structure.

    Vertical memory device with a channel layer in a stacked dielectric layer
    3.
    发明授权
    Vertical memory device with a channel layer in a stacked dielectric layer 有权

    公开(公告)号：US11189636B2

    公开(公告)日：2021-11-30

    申请号：US16870082

    申请日：2020-05-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji Hoon Choi ,  Sung Gil Kim ,  Seulye Kim ,  Jung Ho Kim ,  Hong Suk Kim ,  Phil Ouk Nam ,  Jae Young Ahn ,  Han Jin Lim

    IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565

    Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

    Semiconductor device including dielectric layer
    4.
    发明授权
    Semiconductor device including dielectric layer 有权

    公开(公告)号：US10651194B2

    公开(公告)日：2020-05-12

    申请号：US16142637

    申请日：2018-09-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji Hoon Choi ,  Sung Gil Kim ,  Seulye Kim ,  Jung Ho Kim ,  Hong Suk Kim ,  Phil Ouk Nam ,  Jae Young Ahn ,  Han Jin Lim

    IPC: H01L29/792 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11565

    Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

    Three-dimensional semiconductor memory devices
    5.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US11711920B2

    公开(公告)日：2023-07-25

    申请号：US17076306

    申请日：2020-10-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggil Kim ,  Seulye Kim ,  Jung-Hwan Kim

    IPC: H01L27/11582 ,  H10B43/27 ,  H10B41/27 ,  H01L21/02

    CPC classification number: H10B43/27 ,  H10B41/27 ,  H01L21/02233

    Abstract: A semiconductor memory device includes a substrate with a cell array region and a connection region, an electrode structure including electrodes stacked on the substrate and having a staircase structure on the connection region, a vertical channel structure on the cell array region to penetrate the electrode structure and electrically connected to the substrate, a dummy structure on the connection region to penetrate the staircase structure, and a first sidewall oxide pattern interposed between the substrate and the dummy structure. The dummy structure includes an upper portion that is on the substrate, a middle portion that is in contact with the first sidewall oxide pattern, and a lower portion that is below the middle portion. With increasing vertical distance from the upper portion, a diameter of the middle portion decreases until it reaches its smallest value and then increases.

    Vertical semiconductor devices
    6.
    发明授权
    Vertical semiconductor devices 有权

    公开(公告)号：US11430800B2

    公开(公告)日：2022-08-30

    申请号：US16839184

    申请日：2020-04-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunggil Kim ,  Seulye Kim ,  Dongkyum Kim ,  Sungjin Kim ,  Junghwan Kim ,  Chanhyoung Kim ,  Jihoon Choi

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11558

    Abstract: A vertical semiconductor device may include a stacked structure, a channel structure and a lower connection structure. The stacked structure may include insulation layers and gate electrodes alternately repeatedly stacked. The stacked structure may be spaced apart from an upper surface of a substrate. The channel structure may include a charge storage structure and a channel. The channel structure may pass through the stacked structure. The lower connection structure may be formed on the substrate. The lower connection structure may be electrically connected with the channel and the substrate. A sidewall of the lower connection structure may include a protrusion disposed at a central portion of the sidewall from the upper surface of the substrate in a vertical direction. The vertical semiconductor device may have a high reliability.

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