公开(公告)号：US20240324193A1

公开(公告)日：2024-09-26

申请号：US18515449

申请日：2023-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MinKyung KIM ,  Hakseon Kim ,  Sunggil Kim ,  Jumi Bak ,  Kang-Oh Yun ,  Dongjin Lee ,  Sohyun Lee ,  Junhee Lim

IPC: H10B41/35 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B41/35 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06524

Abstract: A semiconductor device includes a substrate, a doped region on the substrate, the doped region including impurities of a first conductivity type at a first concentration, a gate structure on the substrate, and a first contact electrically connected to the doped region, the first contact including a first portion, a second portion on the first portion, and a third portion on the second portion, the first portion and the second portion including poly silicon, the third portion including at least one metallic material, and the second portion including impurities of the first conductivity type at a second concentration higher than the first concentration.

公开(公告)号：US20230402454A1

公开(公告)日：2023-12-14

申请号：US18133977

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin Lee ,  Junhee Lim ,  Kangoh Yun ,  Sohyun Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/76232

Abstract: A semiconductor device includes a first isolation structure extending through an upper portion of a substrate and defining a first active region, a first gate structure on the substrate, and first source/drain regions at upper portions of the first active region adjacent to the first gate structure. The first isolation structure includes an upper isolation pattern structure and a lower isolation pattern. The upper isolation pattern structure includes a first isolation pattern and a second isolation pattern covering a sidewall of the first isolation pattern. The lower isolation pattern is formed under and contacting the upper isolation pattern structure, and a width of the lower isolation pattern is greater than a width of the upper isolation pattern structure.

公开(公告)号：US20240196622A1

公开(公告)日：2024-06-13

申请号：US18514436

申请日：2023-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangoh Yun ,  Sohyun Lee ,  Dongjin Lee ,  Junhee Lim

IPC: H10B43/40 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/41 ,  H10B80/00

CPC classification number: H10B43/40 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/41 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes a substrate including an active region including a central active region extending in a first direction and first to fourth extended active regions extending from an edge of the central active region in a second direction perpendicular to the first direction, and a device isolation layer defining the active region; and first to fourth gate structures on the active region and spaced apart from one another, wherein the central active region, the first to fourth extended active regions, and the first to fourth gate structures constitute first to fourth pass transistors, the first to fourth pass transistors share one drain region on the central active region, and the active region has an H shape in a plan view.