公开(公告)号：US10103170B2

公开(公告)日：2018-10-16

申请号：US15784635

申请日：2017-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byong-hyun Jang ,  Dongchul Yoo ,  Woojin Jang ,  Jaeyoung Ahn ,  Junkyu Yang

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  H01L29/51 ,  H01L27/11568 ,  H01L21/311 ,  H01L21/28 ,  H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L27/11565

Abstract: A semiconductor device includes word lines vertically stacked on top of each other on a substrate, insulating patterns between the word lines, a vertical pillar connected to the substrate, and residual sacrificial patterns on the substrate at sides of the word lines. The vertical pillar penetrates the word lines and the insulating patterns. Each of the insulating patterns includes a first portion between the word lines and a second portion extending from the first portion and between the residual sacrificial patterns. A first thickness of the first portion is smaller than a second thickness of the second portion.

公开(公告)号：US09653565B2

公开(公告)日：2017-05-16

申请号：US14865078

申请日：2015-09-25

Applicant: Samsung Electronics Co., Ltd

Inventor： Byong-hyun Jang ,  Dongchul Yoo ,  Jaeyoung Ahn ,  Hunhyeong Lim

IPC: H01L29/49 ,  H01L27/11582

CPC classification number: H01L29/495 ,  H01L27/11582

Abstract: A three dimensional semiconductor memory device includes a vertical channel structure extending in a vertical direction on a substrate; interlayer insulating layers surrounding the vertical channel structure and being stacked in the vertical direction on the substrate, gate electrodes surrounding the vertical channel structure and being disposed between the interlayer insulating layers, corners of the gate electrodes adjacent to the vertical channel structure being rounded, and auxiliary gate insulating patterns disposed between the gate electrodes and the vertical channel structure, wherein a side surface of the auxiliary gate insulating pattern is substantially coplanar with a side surface of the interlayer insulating layer in the vertical direction on the substrate.

公开(公告)号：US09130054B2

公开(公告)日：2015-09-08

申请号：US13800872

申请日：2013-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byong-hyun Jang ,  Juhyung Kim ,  Woonkyung Lee ,  Jaegoo Lee ,  Chaeho Kim ,  Junkyu Yang ,  Phil Ouk Nam ,  Jaeyoung Ahn ,  Kihyun Hwang

IPC: H01L21/20 ,  H01L29/792 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/792 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

Abstract translation: 一种半导体存储器件及其制造方法。 该器件包括垂直堆叠在衬底的顶表面上的多个栅极，该衬底的顶表面上形成有在该衬底中形成的外延层，垂直穿过该栅极的垂直沟道以与该外延层电连接;以及存储层，设置在该垂直沟道 和大门。 外延层具有位于最下面一个栅极的底表面和基板的顶表面之间的高度的顶表面。