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    HEAT EXCHANGER AND METHOD OF MANUFACTURING THE SAME, AND OUTDOOR UNIT FOR AIR CONDITIONER HAVING THE HEAT EXCHANGER
    2.
    发明申请
    HEAT EXCHANGER AND METHOD OF MANUFACTURING THE SAME, AND OUTDOOR UNIT FOR AIR CONDITIONER HAVING THE HEAT EXCHANGER 审中-公开
    热交换器及其制造方法和具有热交换器的空调器的室外单元

    公开(公告)号：US20150260436A1

    公开(公告)日：2015-09-17

    申请号：US14642964

    申请日：2015-03-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hong Suk Kim ,  Myong Jong Kwon ,  Seung Jin Oh

    IPC: F25B39/02 ,  B23P15/26

    CPC classification number: F25B39/022 ,  B23P15/26 ,  F28D1/0477 ,  F28D2021/0071 ,  F28F1/32 ,  F28F17/00 ,  F28F19/02 ,  F28F2215/00 ,  F28F2245/02 ,  Y10T29/4935

    Abstract: A heat exchanger having an improved structure in which heat-exchanging efficiency can be improved includes: a refrigerant pipe through which a refrigerant flows; and a plurality of fins that are coupled to an outer circumferential surface of the refrigerant pipe, wherein the plurality of fins include: a first region formed downstream in a direction in which air flows; and a second region formed upstream in the direction in which air flows, and at least one coating layer is formed in the first region and the second region, and thicknesses of the first region and the second region are different from each other.

    Abstract translation: 具有能够提高热交换效率的改进结构的热交换器包括：制冷剂流过的制冷剂管; 以及多个翅片，其联接到所述制冷剂管的外周表面，其中所述多个翅片包括：沿空气流动的方向的下游形成的第一区域; 以及在空气流动的方向上游形成的第二区域，并且在所述第一区域和所述第二区域中形成至少一个涂层，并且所述第一区域和所述第二区域的厚度彼此不同。

    Semiconductor device including dielectric layer
    6.
    发明授权
    Semiconductor device including dielectric layer 有权

    公开(公告)号：US10090323B2

    公开(公告)日：2018-10-02

    申请号：US15484339

    申请日：2017-04-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji Hoon Choi ,  Sung Gil Kim ,  Seulye Kim ,  Jung Ho Kim ,  Hong Suk Kim ,  Phil Ouk Nam ,  Jae Young Ahn ,  Han Jin Lim

    IPC: H01L29/792 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11565

    Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

    Semiconductor memory devices
    8.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US10263006B2

    公开(公告)日：2019-04-16

    申请号：US15480983

    申请日：2017-04-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung Gil Kim ,  Ji-Hoon Choi ,  Dongkyum Kim ,  Jintae Noh ,  Seulye Kim ,  Hong Suk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/08 ,  H01L29/10 ,  H01L27/1157 ,  H01L29/423

    Abstract: A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.

    Vertical memory device with a channel layer in a stacked dielectric layer
    10.
    发明授权
    Vertical memory device with a channel layer in a stacked dielectric layer 有权

    公开(公告)号：US11189636B2

    公开(公告)日：2021-11-30

    申请号：US16870082

    申请日：2020-05-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji Hoon Choi ,  Sung Gil Kim ,  Seulye Kim ,  Jung Ho Kim ,  Hong Suk Kim ,  Phil Ouk Nam ,  Jae Young Ahn ,  Han Jin Lim

    IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565

    Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

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