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    Scan flip-flop, flip-flop and scan test circuit including the same
    3.
    发明授权
    Scan flip-flop, flip-flop and scan test circuit including the same 有权

    公开(公告)号：US11223344B2

    公开(公告)日：2022-01-11

    申请号：US16993946

    申请日：2020-08-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Raheel Azmat ,  Jaehyoung Lim ,  Taehyung Kim ,  Jinwoo Jeong ,  Jaeseok Yang

    IPC: H03K3/037 ,  G01R31/317 ,  G01R31/3177

    Abstract: A scan flip-flop includes a multiplexer, a first latch, a second latch, an output buffer and a clock buffer. The multiplexer selects one of a data input signal and a scan input signal based on an operation mode. The first latch latches an output of the multiplexer. The second latch latches an output of the first latch. The output buffer generates an output signal based on an output of the second latch. The clock buffer generates a first clock signal and a second clock signal that control operation of the first latch and the second latch. The first latch, the second latch, and the clock buffer are sequentially arranged along a first direction. A first clock line supplying the first clock signal and a second clock line supplying the second clock signal have a cross couple connection.

    SCAN FLIP-FLOP, FLIP-FLOP AND SCAN TEST CIRCUIT INCLUDING THE SAME
    5.
    发明申请
    SCAN FLIP-FLOP, FLIP-FLOP AND SCAN TEST CIRCUIT INCLUDING THE SAME 有权

    公开(公告)号：US20210152162A1

    公开(公告)日：2021-05-20

    申请号：US16993946

    申请日：2020-08-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Raheel Azmat ,  Jaehyoung Lim ,  Taehyung Kim ,  Jinwoo Jeong ,  Jaeseok Yang

    IPC: H03K3/037 ,  G01R31/3177 ,  G01R31/317

    Abstract: A scan flip-flop includes a multiplexer, a first latch, a second latch, an output buffer and a clock buffer. The multiplexer selects one of a data input signal and a scan input signal based on an operation mode. The first latch latches an output of the multiplexer. The second latch latches an output of the first latch. The output buffer generates an output signal based on an output of the second latch. The clock buffer generates a first clock signal and a second clock signal that control operation of the first latch and the second latch. The first latch, the second latch, and the clock buffer are sequentially arranged along a first direction. Each of the multiplexer and the output buffer is adjacent the first latch, the second latch, or the clock buffer along a second direction intersecting the first direction. A first clock line supplying the first clock signal and a second clock line supplying the second clock signal have a cross couple connection.

    Semiconductor device and method of fabricating the same
    8.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US11551978B2

    公开(公告)日：2023-01-10

    申请号：US17089822

    申请日：2020-11-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Hun Kim ,  Jaeseok Yang ,  Haewang Lee

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L27/088

    Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11387234B2

    公开(公告)日：2022-07-12

    申请号：US16910385

    申请日：2020-06-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taehyung Kim ,  Panjae Park ,  Jaeseok Yang

    IPC: H01L27/092 ,  H01L23/528 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

    Abstract: A semiconductor device includes a substrate with a first active region; first and second active patterns extending in a first direction and spaced apart in a second direction, and each having a source pattern, a channel pattern, and a drain pattern that are sequentially stacked; first and second gate electrodes that surround the channel patterns of the first and second active patterns and extend in the first direction; an interlayer dielectric layer that covers the first and second active patterns and the first and second gate electrodes; a first active contact that penetrates the interlayer dielectric layer and is coupled to the first active region between the first and second active patterns; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first and second active patterns including an overlapping region that vertically overlaps the first power rail.

    Semiconductor device and method of fabricating the same
    10.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US10861747B2

    公开(公告)日：2020-12-08

    申请号：US16439860

    申请日：2019-06-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Hun Kim ,  Jaeseok Yang ,  Haewang Lee

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L27/088

    Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.

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