公开(公告)号：US20240071545A1

公开(公告)日：2024-02-29

申请号：US18302034

申请日：2023-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjun Oh ,  Seong Geon Lee ,  Dae-Won Kim ,  Kyungduk Lee ,  Youn-Soo Cheon

IPC: G11C29/12 ,  G11C29/42

CPC classification number: G11C29/12005 ,  G11C29/42 ,  G11C2029/1202

Abstract: A method of operating a memory device includes reading a first page of memory cells containing at least one worn-out memory cell therein using a read voltage, from a first memory block, and reading a second page of memory cells, which extends adjacent to the first page in the first memory block, using the read voltage. An operation is performed to determine a match rate between a position of a column including a “0” bit in the first page with a position of a column including a “0” bit in the second page. Thereafter, the second page is read by adjusting a read pass voltage applied to a word line of another page in the first memory block, when the match rate exceeds a threshold match rate.

公开(公告)号：US09768053B2

公开(公告)日：2017-09-19

申请号：US14955193

申请日：2015-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Won Kim ,  Jae-Kyu Lee

IPC: H01L27/24 ,  H01L45/00 ,  H01L21/762 ,  H01L21/308 ,  H01L27/108

CPC classification number: H01L21/762 ,  H01L21/3083 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/2436 ,  H01L27/2463 ,  H01L29/4236 ,  H01L29/78 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A method of forming patterns of a semiconductor device, including partially etching an upper portion of a substrate to form first preliminary active patterns and a first trench, each of the first preliminary active patterns having a first width, and the first trench having a second width of about 2 to 3 times the first width; forming an insulating spacer on each sidewall of the first trench to form a second trench having the first width; forming a second preliminary active pattern in the second trench, the second preliminary active pattern having the first width; partially etching the first and second preliminary active patterns to form a plurality of first active patterns and a plurality of second active patterns and an opening between the plurality of first and second active patterns; and forming an insulation pattern to fill the opening.

公开(公告)号：US10319338B2

公开(公告)日：2019-06-11

申请号：US14611681

申请日：2015-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Myung Lee ,  Dae-Hee Kim ,  Seung-Hwan Jeong ,  Dae-Won Kim ,  Jee-Yeun Wang

IPC: G09G5/02 ,  G09G3/20 ,  G06T11/00 ,  G06T7/90 ,  G06T7/194

Abstract: An electronic device and a method of extracting a color in the electronic device are provided. The electronic device includes a display unit configured to display an image and a controller configured to extract at least one color value from the image, and to extract a color value satisfying a range of color deviation from the extracted color values.

公开(公告)号：US10373693B2

公开(公告)日：2019-08-06

申请号：US15926419

申请日：2018-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Soo Cha ,  Young-Seop Shim ,  Dae-Won Kim

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/26 ,  G06F13/40 ,  G06F13/16 ,  G11C11/56 ,  G11C13/00

Abstract: A method of operating a storage device includes: performing a background read operation on a nonvolatile memory by using a default read voltage level; performing a read retry operation on the nonvolatile memory by using a corrected read voltage level when the background read operation fails; storing the corrected read voltage level in a history buffer when the read retry operation succeeds; and performing a host read operation on the nonvolatile memory by using the history buffer in response to a read request received from a host.

公开(公告)号：US09812539B2

公开(公告)日：2017-11-07

申请号：US14962003

申请日：2015-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Jun Kim ,  Sung-In Kim ,  Jung-Woo Song ,  Jae-Rok Kahng ,  Dae-Won Kim

IPC: H01L29/423 ,  H01L27/108 ,  H01L27/24 ,  H01L29/66 ,  H01L21/768 ,  H01L21/74 ,  H01L27/22 ,  H01L43/08 ,  H01L45/00 ,  H01L21/285

CPC classification number: H01L29/4236 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/228 ,  H01L27/2436 ,  H01L29/66621 ,  H01L43/08 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/144

Abstract: Semiconductor devices are provided including a substrate defining a gate trench. A buried gate structure is provided in the gate trench and at least fills the gate trench. The buried gate structure includes a gate insulation layer pattern, a gate electrode and a capping layer pattern. First and second impurity regions are provided at portions of the substrate adjacent to the buried gate structure, respectively. At least a portion of each of the first and second impurity regions face a sidewall of the buried gate structure. First and second buried contact structures are provided on the first and second impurity regions, respectively. Each of the first and second buried contact structures includes a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures face to a sidewall of the buried gate structure.

公开(公告)号：USD745543S1

公开(公告)日：2015-12-15

申请号：US29456524

申请日：2013-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Dae-Won Kim ,  Chang-Mo Yang ,  Jee-Yeun Wang ,  In-Won Jong

公开(公告)号：USD735741S1

公开(公告)日：2015-08-04

申请号：US29434365

申请日：2012-10-12

Applicant: Samsung Electronics Co., Ltd.

Designer： Dae-Won Kim

公开(公告)号：US10374087B2

公开(公告)日：2019-08-06

申请号：US14956908

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Won Kim ,  Jae-Kyu Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/22 ,  H01L21/762

Abstract: A semiconductor device includes a substrate, first and second isolation layers, an insulation layer pattern, and a gate structure. The substrate has a cell region and a peripheral region. The first isolation layer is buried in a first upper portion of the substrate in the peripheral region. The second isolation layer is buried in a second upper portion of the substrate in the cell region, and extends along a first direction substantially parallel to a top surface of the substrate. The insulation layer pattern is buried in the first upper portion, and extends along a second direction substantially parallel to the top surface of the substrate and substantially perpendicular to the first direction. The insulation layer pattern has a lower surface higher than a lower surface of the second isolation layer, and applies a stress to a portion of the substrate adjacent thereto.

公开(公告)号：US09378815B2

公开(公告)日：2016-06-28

申请号：US14878629

申请日：2015-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Kyu Lee ,  Dae-Won Kim

IPC: G11C11/00 ,  G11C7/00 ,  G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/76 ,  G11C2213/79

Abstract: A resistive memory device includes a memory cell array having a plurality of memory cells therein, which operate in response to word line driving and column selecting signals. Each of memory cells includes a resistive device and a cell transistor connected in series. An I/O sense amplifier senses and amplifies data output from the memory cell array to thereby generate output data, and also generate program current based on input data and provide the program current to the memory cell array. The resistive memory device is also configured to read output data from the I/O sense amplifier and adjust interface states of the cell transistors based on a voltage level of the output data during a test mode.

Abstract translation: 电阻式存储器件包括其中具有多个存储单元的存储单元阵列，其响应于字线驱动和列选择信号而工作。 每个存储单元包括串联连接的电阻器件和单元晶体管。 I / O读出放大器感测并放大从存储单元阵列输出的数据，从而生成输出数据，并且还根据输入数据生成程序电流，并将程序电流提供给存储单元阵列。 电阻性存储器件还被配置为从I / O读出放大器读取输出数据，并且在测试模式期间基于输出数据的电压电平来调节单元晶体管的接口状态。