公开(公告)号：US11152374B2

公开(公告)日：2021-10-19

申请号：US16171517

申请日：2018-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-A Kim ,  Yong-Kwan Kim ,  Se-Keun Park ,  Jung-Woo Song ,  Joo-Young Lee

IPC: H01L27/108 ,  H01L21/768

Abstract: A semiconductor device includes a bit line structure on a substrate, a spacer structure including a first spacer directly contacting a sidewall of the bit line structure, a second spacer directly contacting a portion of an outer sidewall of the first spacer, the second spacer including air, and a third spacer directly contacting an upper portion of the first spacer and covering an outer sidewall and an upper surface of the second spacer, and a contact plug structure extending in a vertical direction substantially perpendicular to an upper surface of the substrate and directly contacting an outer sidewall of the third spacer at least at a height between respective heights of a bottom and a top surface of the second spacer.

公开(公告)号：US09812539B2

公开(公告)日：2017-11-07

申请号：US14962003

申请日：2015-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Jun Kim ,  Sung-In Kim ,  Jung-Woo Song ,  Jae-Rok Kahng ,  Dae-Won Kim

IPC: H01L29/423 ,  H01L27/108 ,  H01L27/24 ,  H01L29/66 ,  H01L21/768 ,  H01L21/74 ,  H01L27/22 ,  H01L43/08 ,  H01L45/00 ,  H01L21/285

CPC classification number: H01L29/4236 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/228 ,  H01L27/2436 ,  H01L29/66621 ,  H01L43/08 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/144

Abstract: Semiconductor devices are provided including a substrate defining a gate trench. A buried gate structure is provided in the gate trench and at least fills the gate trench. The buried gate structure includes a gate insulation layer pattern, a gate electrode and a capping layer pattern. First and second impurity regions are provided at portions of the substrate adjacent to the buried gate structure, respectively. At least a portion of each of the first and second impurity regions face a sidewall of the buried gate structure. First and second buried contact structures are provided on the first and second impurity regions, respectively. Each of the first and second buried contact structures includes a metal silicide pattern and a metal pattern, and at least a portion of each of the first and second buried contact structures face to a sidewall of the buried gate structure.