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    Vertical semiconductor device
    2.
    发明授权
    Vertical semiconductor device 有权

    公开(公告)号：US12278182B2

    公开(公告)日：2025-04-15

    申请号：US17721481

    申请日：2022-04-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changyeon Yu ,  Pansuk Kwak ,  Daeseok Byeon

    IPC: H01L23/528 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

    Abstract: A vertical memory device may include a first conductive line structure and an address decoder. The first conductive line structure may be on a substrate. The first conductive line structure may include conductive lines and insulation layers alternately and repeatedly stacked in a direction perpendicular to the substrate. The address decoder may be connected to a first end of each of conductive lines included in the first conductive line structure. The address decoder may apply electrical signal to the conductive lines. In each of the conductive lines, a first portion adjacent to the first end and a second portion adjacent to a second end may have different shapes. A first resistance in the first portion may be lower than a second resistance in the second portion. RC delay of the conductive lines may be reduced.

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12002512B2

    公开(公告)日：2024-06-04

    申请号：US17709910

    申请日：2022-03-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changyeon Yu ,  Pansuk Kwak ,  Daeseok Byeon

    IPC: G11C16/00 ,  G11C16/04 ,  G11C16/08

    CPC classification number: G11C16/0483 ,  G11C16/08

    Abstract: A semiconductor device includes a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including select transistors and memory cells; pass transistors configured to provide select signals to select lines connected to a selected memory block; and ground transistors configured to supply a first voltage to select lines connected to unselected memory blocks. The ground transistors include at least one common gate structure, at least one common active region, and individual active regions, and each of the common gate structure and the common active region are shared by two or more ground transistors, among the ground transistors. The common gate structure is between the common active region and the individual active regions, and includes a first region extending in a first direction and a second region extending in a second direction, intersecting the first direction.

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250157496A1

    公开(公告)日：2025-05-15

    申请号：US18791587

    申请日：2024-08-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taemin Ok ,  Changyeon Yu ,  Pansuk Kwak

    IPC: G11C5/06 ,  G11C16/04 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

    Abstract: A semiconductor device includes a plurality of blocks each including a first substrate, a plurality of lower gate electrode layers stacked in a first direction perpendicular to an upper surface of the first substrate, a second substrate above the plurality of lower gate electrode layers, and a plurality of upper gate electrode layers stacked in the first direction on the second substrate; pass transistors electrically connected to the plurality of lower gate electrode layers and the plurality of upper gate electrode layers; and a row decoder electrically connected to the pass transistors, wherein a number of the plurality of lower gate electrode layers and a number of the plurality of upper gate electrode layers included in each of the plurality of blocks are greater than a number of the pass transistors.

    Integrated circuit including power gating circuit
    6.
    发明授权
    Integrated circuit including power gating circuit 有权

    公开(公告)号：US12249984B2

    公开(公告)日：2025-03-11

    申请号：US17886194

    申请日：2022-08-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Changyeon Yu ,  Pansuk Kwak ,  Daeseok Byeon

    IPC: H01L27/02 ,  G06F1/26 ,  H03K17/687 ,  H03K19/00 ,  H03K19/003

    Abstract: An integrated circuit includes a logic circuit comprising a plurality of logic transistors, the logic circuit comprising a plurality of logic gate lines extending in a first direction; and a power gating circuit comprising a plurality of power gating transistors, the power gating circuit comprising a first power gate line extending in a second direction that is perpendicular to the first direction, and the power gating circuit being connected to the logic circuit, wherein a plurality of source regions respectively included in the plurality of power gating transistors are connected to each other, or a plurality of drain regions respectively included in the plurality of power gating transistors are connected to each other.

    NONVOLATILE MEMORY DEVICE HAVING CELL ON PERIPHERY STRUCTURE
    8.
    发明申请
    NONVOLATILE MEMORY DEVICE HAVING CELL ON PERIPHERY STRUCTURE 有权

    公开(公告)号：US20220115393A1

    公开(公告)日：2022-04-14

    申请号：US17345832

    申请日：2021-06-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Changyeon Yu ,  Pansuk Kwak

    IPC: H01L27/11573 ,  H01L21/66 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

    Abstract: A nonvolatile memory device having a cell over periphery (COP) structure includes a first sub memory plane and a second sub memory plane disposed adjacent to the first sub memory plane a row direction. A first vertical contact region is disposed in the cell region of the first sub memory plane and a second vertical contact region is disposed in the cell region of the second sub memory plane. A first overhead region is disposed in the cell region of the first sub memory plane and adjacent to the second vertical region in the row direction, and a second overhead region is disposed in the cell region of the second sub memory plane and adjacent the first vertical region in the row direction. Cell channel structures are disposed in a main region of the cell region.

    THREE-DIMENSIONAL MEMORY DEVICE
    9.
    发明公开
    THREE-DIMENSIONAL MEMORY DEVICE 审中-公开

    公开(公告)号：US20240306394A1

    公开(公告)日：2024-09-12

    申请号：US18434356

    申请日：2024-02-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungun Lee ,  Pansuk Kwak ,  Changyeon Yu

    IPC: H10B43/40 ,  G11C16/08 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

    CPC classification number: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  G11C16/08

    Abstract: A memory device includes a stack structure, in which a common source line is formed, and a peripheral circuit structure overlapping the stack structure when viewed in plan view and comprising a common source line driver configured to discharge the common source line. The common source line driver includes a first common source line driving unit, electrically connected to the common source line through a first network and configured to discharge the common source line, and a second common source line driving unit electrically connected to the common source line through a second network, different from the first network, and configured to discharge the common source line. The first common source line driving unit and the second common source line driving unit are controlled independently of each other.

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