公开(公告)号：US11862624B2

公开(公告)日：2024-01-02

申请号：US17325821

申请日：2021-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Ok ,  Inmo Kim ,  Sujeong Kim ,  Daeseok Byeon

IPC: H01L27/02 ,  H01L23/538 ,  H01L27/06 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L27/0255 ,  H01L23/5384 ,  H01L23/5386 ,  H01L27/0629 ,  H10B41/27 ,  H10B43/27

Abstract: An integrated circuit device includes a semiconductor substrate having components of a peripheral circuit structure formed in and on a surface of the semiconductor substrate. The peripheral circuit structure comprising a plurality of protective antenna diodes therein. A memory cell array structure is provided on at least a portion of the peripheral circuit structure. A charge accumulating conductive plate is provided, which extends between the peripheral circuit structure and the memory cell array structure. The conductive plate is electrically connected to current carrying terminals of the antenna diodes within the peripheral circuit structure. The conductive plate may have a generally rectangular planar shape with four corners, and the antenna diodes may be arranged into four groups, which extend between respective corners of the conductive plate and the semiconductor substrate.

公开(公告)号：US20250157496A1

公开(公告)日：2025-05-15

申请号：US18791587

申请日：2024-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Ok ,  Changyeon Yu ,  Pansuk Kwak

IPC: G11C5/06 ,  G11C16/04 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a plurality of blocks each including a first substrate, a plurality of lower gate electrode layers stacked in a first direction perpendicular to an upper surface of the first substrate, a second substrate above the plurality of lower gate electrode layers, and a plurality of upper gate electrode layers stacked in the first direction on the second substrate; pass transistors electrically connected to the plurality of lower gate electrode layers and the plurality of upper gate electrode layers; and a row decoder electrically connected to the pass transistors, wherein a number of the plurality of lower gate electrode layers and a number of the plurality of upper gate electrode layers included in each of the plurality of blocks are greater than a number of the pass transistors.

公开(公告)号：US11961560B2

公开(公告)日：2024-04-16

申请号：US17096245

申请日：2020-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myunghun Lee ,  Sangwan Nam ,  Taemin Ok

IPC: H01L23/528 ,  G11C16/04 ,  G11C16/26 ,  H10B41/27 ,  H10B41/40 ,  H10B41/50 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

CPC classification number: G11C16/0483 ,  G11C16/26 ,  H01L23/528 ,  H10B41/27 ,  H10B41/40 ,  H10B41/50 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

Abstract: An integrated circuit device includes a peripheral circuit structure including a lower substrate, an arc protection diode in the lower substrate, and a common source line driver connected to the arc protection diode, a conductive plate on the peripheral circuit structure, a cell array structure overlapping the peripheral circuit structure in a vertical direction with the conductive plate therebetween, and a first wiring structure connected between the arc protection diode and the conductive plate.

公开(公告)号：US20220139904A1

公开(公告)日：2022-05-05

申请号：US17325821

申请日：2021-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Ok ,  Inmo Kim ,  Sujeong Kim ,  Daeseok Byeon

IPC: H01L27/02 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/06 ,  H01L23/538

Abstract: An integrated circuit device includes a semiconductor substrate having components of a peripheral circuit structure formed in and on a surface of the semiconductor substrate. The peripheral circuit structure comprising a plurality of protective antenna diodes therein. A memory cell array structure is provided on at least a portion of the peripheral circuit structure. A charge accumulating conductive plate is provided, which extends between the peripheral circuit structure and the memory cell array structure. The conductive plate is electrically connected to current carrying terminals of the antenna diodes within the peripheral circuit structure. The conductive plate may have a generally rectangular planar shape with four corners, and the antenna diodes may be arranged into four groups, which extend between respective corners of the conductive plate and the semiconductor substrate.