公开(公告)号：US09854650B2

公开(公告)日：2017-12-26

申请号：US15228576

申请日：2016-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Seob Kim ,  Chang Hoon Baek ,  Ho Chan Cho ,  Seung Kwan Choi

IPC: H05B37/02 ,  F21V29/74 ,  F21K9/275 ,  F21K9/278 ,  F21K9/238 ,  F21K9/235 ,  F21V7/00 ,  F21V19/00 ,  F21V23/00 ,  H04B5/00 ,  H04B10/50 ,  H04W4/00 ,  H05B33/08 ,  F21Y115/10

CPC classification number: H05B37/0272 ,  F21K9/235 ,  F21K9/238 ,  F21K9/275 ,  F21K9/278 ,  F21V7/0008 ,  F21V19/006 ,  F21V23/005 ,  F21V29/74 ,  F21Y2115/10 ,  H04B5/0031 ,  H04B10/116 ,  H04B10/502 ,  H04W4/80 ,  H05B33/0854 ,  H05B33/0872 ,  H05B37/0218 ,  H05B37/0227

Abstract: A lighting system includes a plurality of lighting devices including a controller transmitting and receiving data by using near field communications (NFC) The lighting system further includes a control device that collects identification information for the plurality of respective lighting devices through the NFC communications before the plurality of lighting devices are installed. The control device also generates settings data to control the plurality of lighting devices, based on the identification information, and then transmits the generated settings data to the plurality of respective lighting devices.

公开(公告)号：US09432028B2

公开(公告)日：2016-08-30

申请号：US14716106

申请日：2015-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Jin Kim ,  Chang Hoon Baek ,  Sang Kyu Lee ,  Jae Youl Lee

IPC: H03D3/24 ,  H03L7/08 ,  H03L7/089 ,  H03L7/093 ,  H03L7/091 ,  H03L7/099 ,  H03L7/187

CPC classification number: H03L7/0807 ,  H03L1/00 ,  H03L7/087 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/0995 ,  H03L7/113 ,  H03L7/187 ,  H03L2207/06 ,  H03L2207/50

Abstract: A clock data recovery circuit including: a digital phase detector and deserializer configured to sample serial data using a recovery clock signal to generate an up phase error signal and a down phase error signal which correspond to a phase difference between the serial data and the recovery clock signal; a digital loop filter configured to generate an up fine code and a down fine code based on a result of counting the up and down phase error signals; a loop combiner configured to generate an up fine tuning code and a down fine tuning code by using the up and down phase error signals and the up and down fine codes; and a digitally controlled oscillator configured to generate the recovery clock signal having a frequency changed with the up and down fine tuning codes.

Abstract translation: 一种时钟数据恢复电路，包括：数字相位检测器和解串器，被配置为使用恢复时钟信号对串行数据进行采样，以产生对应于串行数据和恢复时钟之间的相位差的上相位误差信号和下行相位误差信号 信号; 数字环路滤波器，其被配置为基于对所述上下相位误差信号进行计数的结果来生成上位编码和下精细码; 配置为通过使用上下相位误差信号和上下精细码产生上调微调码和下调微调码的环路组合器; 以及数字控制振荡器，被配置为产生具有随着上下微调代码而改变的频率的恢复时钟信号。

公开(公告)号：US10764976B2

公开(公告)日：2020-09-01

申请号：US16055950

申请日：2018-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Seob Kim ,  Chang Hoon Baek

IPC: H05B33/08 ,  H05B37/02 ,  H05B47/10 ,  H05B45/10 ,  G01S13/02 ,  G01S13/56 ,  H05B47/105

Abstract: A lighting device includes an ultra-wideband (UWB) sensor module configured to detect movement, a light source module having a plurality of light emitting diodes (LEDs), and a driver configured to drive the plurality of LEDs, and a first controller connected to the light source module and the UWB sensor module, the first controller being configured to receive setting data from an external control device, output the setting data to the UWB sensor module to cause the UWB sensor module to set at least one operational parameter of the UWB sensor module, and output a control signal to the driver to cause the driver to drive the plurality of LEDs.

公开(公告)号：US20150358024A1

公开(公告)日：2015-12-10

申请号：US14716106

申请日：2015-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Jin KIM ,  Chang Hoon Baek ,  Sang Kyu Lee ,  Jae Youl Lee

IPC: H03L7/08 ,  H03L7/187 ,  H03L7/091 ,  H03L7/099 ,  H03L7/089 ,  H03L7/093

CPC classification number: H03L7/0807 ,  H03L1/00 ,  H03L7/087 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/0995 ,  H03L7/113 ,  H03L7/187 ,  H03L2207/06 ,  H03L2207/50

Abstract: A clock data recovery circuit including: a digital phase detector and deserializer configured to sample serial data using a recovery clock signal to generate an up phase error signal and a down phase error signal which correspond to a phase difference between the serial data and the recovery clock signal; a digital loop filter configured to generate an up fine code and a down fine code based on a result of counting the up and down phase error signals; a loop combiner configured to generate an up fine tuning code and a down fine tuning code by using the up and down phase error signals and the up and down fine codes; and a digitally controlled oscillator configured to generate the recovery clock signal having a frequency changed with the up and down fine tuning codes.

Abstract translation: 一种时钟数据恢复电路，包括：数字相位检测器和解串器，被配置为使用恢复时钟信号对串行数据进行采样，以产生对应于串行数据和恢复时钟之间的相位差的上相位误差信号和下行相位误差信号 信号; 数字环路滤波器，其被配置为基于对所述上下相位误差信号进行计数的结果来生成上位编码和下精细码; 配置为通过使用上下相位误差信号和上下精细码产生上调微调码和下调微调码的环路组合器; 以及数字控制振荡器，被配置为产生具有随着上下微调代码而改变的频率的恢复时钟信号。