公开(公告)号：US20150229302A1

公开(公告)日：2015-08-13

申请号：US14556605

申请日：2014-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Jin KIM ,  Jae Youl LEE

IPC: H03K5/24

CPC classification number: H03K5/2481 ,  H03K5/249

Abstract: A sense amplifier includes a differential input circuit, a floating prevention circuit, and a differential amplifier. The differential input circuit output a first current flowing through a first node according to a first input signal, and second current flowing through a second node according to a second input signal. The floating prevention circuit outputs a third current flowing through the first node according to the second input signal, and fourth current flowing through the second node according to the first input signal. The differential amplifier generates a first output signal according to the first current or the third current flowing through the first node, and a second output signal according to the second current or the fourth current flowing through the second node. The sense amplifier may be coupled to a latch to form a flip-flop circuit.

Abstract translation: 读出放大器包括差分输入电路，浮动防止电路和差分放大器。 差分输入电路根据第一输入信号输出流过第一节点的第一电流，以及根据第二输入信号流过第二节点的第二电流。 浮动防止电路根据第二输入信号输出流过第一节点的第三电流，以及根据第一输入信号流过第二节点的第四电流。 差分放大器根据流过第一节点的第一电流或第三电流产生第一输出信号，以及根据流过第二节点的第二电流或第四电流产生第二输出信号。 读出放大器可以耦合到锁存器以形成触发器电路。

公开(公告)号：US20150358024A1

公开(公告)日：2015-12-10

申请号：US14716106

申请日：2015-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Jin KIM ,  Chang Hoon Baek ,  Sang Kyu Lee ,  Jae Youl Lee

IPC: H03L7/08 ,  H03L7/187 ,  H03L7/091 ,  H03L7/099 ,  H03L7/089 ,  H03L7/093

CPC classification number: H03L7/0807 ,  H03L1/00 ,  H03L7/087 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/0995 ,  H03L7/113 ,  H03L7/187 ,  H03L2207/06 ,  H03L2207/50

Abstract: A clock data recovery circuit including: a digital phase detector and deserializer configured to sample serial data using a recovery clock signal to generate an up phase error signal and a down phase error signal which correspond to a phase difference between the serial data and the recovery clock signal; a digital loop filter configured to generate an up fine code and a down fine code based on a result of counting the up and down phase error signals; a loop combiner configured to generate an up fine tuning code and a down fine tuning code by using the up and down phase error signals and the up and down fine codes; and a digitally controlled oscillator configured to generate the recovery clock signal having a frequency changed with the up and down fine tuning codes.

Abstract translation: 一种时钟数据恢复电路，包括：数字相位检测器和解串器，被配置为使用恢复时钟信号对串行数据进行采样，以产生对应于串行数据和恢复时钟之间的相位差的上相位误差信号和下行相位误差信号 信号; 数字环路滤波器，其被配置为基于对所述上下相位误差信号进行计数的结果来生成上位编码和下精细码; 配置为通过使用上下相位误差信号和上下精细码产生上调微调码和下调微调码的环路组合器; 以及数字控制振荡器，被配置为产生具有随着上下微调代码而改变的频率的恢复时钟信号。

公开(公告)号：US20190087373A1

公开(公告)日：2019-03-21

申请号：US15941607

申请日：2018-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Jin KIM ,  Hyun Wook LIM ,  Seong Young RYU ,  Soo Joo LEE

IPC: G06F13/40 ,  H03K19/0175

Abstract: A termination circuit is provided. The termination device includes terminals configured to receive a corresponding signal; unit circuits respectively connected to the terminals, the unit circuits each including a unit resistor and a unit switch element connected to each other in series; common mode capacitors; first switch elements respectively connected between each of the unit circuits and a first corresponding common mode capacitor of common mode capacitors, each of the first switch elements being configured to turn on when the corresponding signal is received in a first mode; and second switch elements respectively connected between each of the unit circuits and a second corresponding common mode capacitor of the common mode capacitors, the second switch elements being configured to turn on when the corresponding signal is received in a second mode different from the first mode.

公开(公告)号：US20150161000A1

公开(公告)日：2015-06-11

申请号：US14565107

申请日：2014-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hong KIM ,  Tae Jin KIM ,  Ji Sung PARK ,  Sung Jin LEE

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/108 ,  G06F3/0608 ,  G06F3/0641 ,  G06F3/0688 ,  G06F3/0689

Abstract: Provided are a nonvolatile memory device and a deduplication method thereof. The nonvolatile memory device includes a plurality of data storages written in a unit of data block; and a storage controller dividing write-requested data in a unit of data block to generate a plurality of data blocks, determining whether each of predetermined data blocks from among the plurality of data blocks is duplicated, generating parity data with reference to non-duplicated data blocks from among the predetermined data blocks, and controlling the plurality of data storages such that the parity data and the non-duplicated data blocks are written into at least one of the plurality of data storages. Since a deduplication operation is performed before generating parity data to assure reliability of data, the number of write operations is reduced and restoration probability of the nonvolatile memory device increases.

Abstract translation: 提供一种非易失性存储器件及其重复数据删除方法。 非易失性存储器件包括以数据块为单位写入的多个数据存储器; 以及存储控制器，以数据块的单位分割写请求的数据，以生成多个数据块，确定来自多个数据块中的每个预定数据块是否被复制，参考未重复的数据产生奇偶校验数据 并且控制多个数据存储器，使得奇偶校验数据和非复制数据块被写入到多个数据存储器中的至少一个数据存储器中。 由于在产生奇偶校验数据之前执行重复数据删除操作以确保数据的可靠性，所以写入操作的数量减少，并且非易失性存储器件的恢复概率增加。