公开(公告)号：US20150200135A1

公开(公告)日：2015-07-16

申请号：US14667915

申请日：2015-03-25

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi SUNAMURA ,  Naoya INOUE ,  Kishou KANEKO

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L21/76895 ,  H01L21/76849 ,  H01L21/823885 ,  H01L23/49822 ,  H01L27/0688 ,  H01L27/10858 ,  H01L27/1104 ,  H01L27/11551 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.

Abstract translation: 提高了布置在多层布线层中的半导体元件的性能。 半导体器件包括：布置在第一布线层中的第一布线; 布置在层叠在第一布线层上的第二布线层中的第二布线; 栅电极，其在第一布线层和第二布线层的层叠方向上配置在第一布线和第二布线之间，不与第一布线和第二布线相连; 设置在所述栅电极的侧表面上的栅极绝缘膜; 以及通过栅极绝缘膜设置在栅电极的侧表面上并与第一线和第二线耦合的半导体层。

公开(公告)号：US20140187047A1

公开(公告)日：2014-07-03

申请号：US14141042

申请日：2013-12-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masayoshi TAGAMI ,  Naoya INOUE

IPC: H01L21/033 ,  H01L21/308

CPC classification number: H01L21/0337 ,  H01L21/0276 ,  H01L21/31144 ,  H01L21/76816

Abstract: A method for forming a semiconductor device that includes a SiARC layer formed over a photoresist film which is formed over spacer portions which are formed on a spacer assist layer which is formed over a hard mask layer. The SiARC layer has an etch rate substantially similar to the etch rate of the spacer assist layer. The photoresist layer and the SiARC layer are removed from a first region to expose the spacer portions and the spacer assist layer. The SiARC layer in the second region and the exposed spacer assist layer in the first region are simultaneously etched leaving remaining spacer portions and remaining spacer assist layer portions. A part of the hard mask layer is etched to form hard mask portions in the first region using the remaining spacer portions and the remaining spacer assist layer portions as an etching mask.

Abstract translation: 一种用于形成半导体器件的方法，该半导体器件包括在形成在形成在硬掩模层上的间隔辅助层上的间隔部分上形成的光致抗蚀剂膜上形成的SiARC层。 SiARC层具有与间隔辅助层的蚀刻速率基本相似的蚀刻速率。 从第一区域去除光致抗蚀剂层和SiARC层，以露出间隔物部分和间隔辅助层。 第二区域中的SiARC层和第一区域中的暴露的间隔辅助层被同时蚀刻，留下剩余的间隔部分和剩余的间隔辅助层部分。 蚀刻硬膜掩模层的一部分，以使用剩余的间隔物部分和剩余的间隔辅助层部分作为蚀刻掩模在第一区域中形成硬掩模部分。

公开(公告)号：US20150349134A1

公开(公告)日：2015-12-03

申请号：US14822230

申请日：2015-08-10

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi SUNAMURA ,  Naoya INOUE ,  Kishou Kaneko

IPC: H01L29/786 ,  H01L29/22 ,  H01L27/12 ,  H01L23/532 ,  H01L29/24 ,  H01L27/092

CPC classification number: H01L29/7869 ,  H01L23/53228 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/101 ,  H01L27/105 ,  H01L27/1082 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/2436 ,  H01L29/22 ,  H01L29/24 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a readily manufacturable semiconductor device including two transistors having mutually different characteristics. The semiconductor device includes a substrate, a multilayer wiring layer disposed over the substrate, a first transistor disposed in the multilayer wiring layer, and a second transistor disposed in a layer different from a layer including the first transistor disposed therein of the multilayer wiring layer, and having different characteristics from those of the first transistor. This can provide a readily manufacturable semiconductor device including two transistors having mutually different characteristics.

Abstract translation: 提供了包括具有相互不同特性的两个晶体管的容易制造的半导体器件。 半导体器件包括衬底，设置在衬底上的多层布线层，设置在多层布线层中的第一晶体管，以及设置在不同于布置在多层布线层中的第一晶体管的层的层中的第二晶体管， 并具有与第一晶体管不同的特性。 这可以提供包括具有相互不同特性的两个晶体管的容易制造的半导体器件。

公开(公告)号：US20150171120A1

公开(公告)日：2015-06-18

申请号：US14633791

申请日：2015-02-27

Applicant: Renesas Electronics Corporation

Inventor： Kishou KANEKO ,  Naoya INOUE ,  Yoshihiro HAYASHI

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/49 ,  H01L21/465 ,  H01L21/4763 ,  H01L21/02 ,  H01L29/66 ,  H01L21/44

CPC classification number: H01L27/1259 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02565 ,  H01L21/28 ,  H01L21/44 ,  H01L21/465 ,  H01L21/47635 ,  H01L23/522 ,  H01L27/088 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1237 ,  H01L27/124 ,  H01L27/1251 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/66477 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer.

Abstract translation: 形成层间绝缘膜。 然后将第一栅电极和第二栅电极埋入层间绝缘膜中。 然后，在层间绝缘膜上方，在第一栅电极上方和第二栅电极上形成防扩散膜。 然后，在存在于第一栅电极上的抗扩散膜上形成第一半导体层。 然后，在第一半导体层的上表面和横向侧上以及反扩散膜之上形成绝缘覆盖膜。 然后，在绝缘覆盖膜上形成半导体膜。 然后，选择性地去除半导体膜以留下位于第二栅电极上的部分，从而形成第二半导体层。

公开(公告)号：US20150056778A1

公开(公告)日：2015-02-26

申请号：US14516164

申请日：2014-10-16

Applicant: Renesas Electronics Corporation

Inventor： Kenzo MANABE ,  Naoya INOUE ,  Kenichiro HIJIOKA ,  Yoshihiro HAYASHI

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L27/1085 ,  H01L21/768 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.

Abstract translation: 一种半导体器件，包括：多层布线层，位于基板的上方，其中堆叠由布线和绝缘层构成的多个布线层; 存储电路，其形成在所述基板的存储电路区域中，并且具有嵌入在位于所述多层布线层中的凹部的电容元件; 形成在基板的逻辑电路区域中的逻辑电路; 层叠在由下部电极，电容绝缘膜和上部电极构成的电容元件上的上部耦合布线; 以及形成在构成逻辑电路的布线的上表面上的盖层。 上部连接线的上表面和盖膜的上表面设置在同一平面上。

公开(公告)号：US20130153888A1

公开(公告)日：2013-06-20

申请号：US13682297

申请日：2012-11-20

Applicant: Renesas Electronics Corporation

Inventor： Naoya INOUE ,  Kishou KANEKO ,  Yoshihiro HAYASHI

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76814 ,  H01L21/76879 ,  H01L23/522 ,  H01L23/53223 ,  H01L23/5329 ,  H01L28/60 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a semiconductor device provided with an active element in a multilayer interconnect layer and decreased in a chip area. A second interconnect layer is provided over a first interconnect layer. A first interlayer insulating layer is provided in the first interconnect layer. A semiconductor layer is provided in a second interconnect layer and in contact with the first interlayer insulating layer. A gate insulating film is provided over the semiconductor layer. A gate electrode is provided over the gate insulating film. At least two first vias are provided in the first interconnect layer and in contact by way of upper ends thereof with the semiconductor layer.

Abstract translation: 公开了一种半导体器件，其在多层互连层中设置有源元件并且在芯片面积上减小。 在第一互连层上提供第二互连层。 第一层间绝缘层设置在第一互连层中。 半导体层设置在第二互连层中并与第一层间绝缘层接触。 在半导体层上设置栅极绝缘膜。 在栅绝缘膜上设置栅电极。 至少两个第一通孔设置在第一互连层中并且通过其上端与半导体层接触。

公开(公告)号：US20130092993A1

公开(公告)日：2013-04-18

申请号：US13652944

申请日：2012-10-16

Applicant: Renesas Electronics Corporation

Inventor： Kenichiro HIJIOKA ,  Naoya INOUE ,  Yoshihiro HAYASHI

IPC: H01L29/94 ,  H01L21/02

CPC classification number: H01L23/528 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10835 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894 ,  H01L28/91 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact.

Abstract translation: 半导体器件包括衬底，层间绝缘层，第一晶体管，多层互连层，电容器件，金属互连和第一触点。 层间绝缘膜设置在基板上。 将第一晶体管设置在衬底上并埋在层间绝缘层中。 第一晶体管至少具有栅电极和扩散电极。 多层互连层设置在层间绝缘膜的上方。 电容器件设置在多层互连层中。 金属互连与栅电极的上表面接触并埋在层间绝缘层中。 第一触点耦合到第一晶体管的扩散层并且被埋在层间绝缘层中。 金属互连包括与第一接触相同的材料。

公开(公告)号：US20160240625A1

公开(公告)日：2016-08-18

申请号：US15139563

申请日：2016-04-27

Applicant: Renesas Electronics Corporation

Inventor： Naoya INOUE ,  Kishou KANEKO ,  Yoshihiro HAYASHI

IPC: H01L29/423 ,  H01L23/522 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/42384 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02565 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.

Abstract translation: 本发明可以降低半导体元件的导通电阻，而不会妨碍具有使用布线层中的导线的半导体元件作为栅电极的半导体器件中的扩散防止膜的功能，并具有栅极绝缘膜 在与扩散防止膜相同的层中。 第一导线和栅电极嵌入到包括第一布线层的绝缘层的表面层中。 在第一布线层和第二布线层之间形成扩散防止膜。 栅极绝缘膜通过以下方式形成：在与栅电极重叠的区域和区域周围形成在扩散防止膜的上表面上的凹部; 并使部件变薄。

公开(公告)号：US20150056762A1

公开(公告)日：2015-02-26

申请号：US14527019

申请日：2014-10-29

Applicant: Renesas Electronics Corporation

Inventor： Naoya INOUE ,  Kishou KANEKO ,  Yoshihiro HAYASHI

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L29/42384 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02565 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.

Abstract translation: 本发明可以降低半导体元件的导通电阻，而不会妨碍具有使用布线层中的导线的半导体元件作为栅电极的半导体器件中的扩散防止膜的功能，并具有栅极绝缘膜 在与扩散防止膜相同的层中。 第一导线和栅电极嵌入到包括第一布线层的绝缘层的表面层中。 在第一布线层和第二布线层之间形成扩散防止膜。 栅极绝缘膜通过以下方式形成：在与栅电极重叠的区域和区域周围形成在扩散防止膜的上表面上的凹部; 并使部件变薄。

公开(公告)号：US20140295657A1

公开(公告)日：2014-10-02

申请号：US14300836

申请日：2014-06-10

Applicant: Renesas Electronics Corporation

Inventor： Naoya INOUE ,  Kishou KANEKO ,  Yoshihiro HAYASHI

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/76879 ,  H01L23/522 ,  H01L23/53223 ,  H01L23/5329 ,  H01L28/60 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a semiconductor device provided with an active element in a multilayer interconnect layer and decreased in a chip area. A second interconnect layer is provided over a first interconnect layer. A first interlayer insulating layer is provided in the first interconnect layer. A semiconductor layer is provided in a second interconnect layer and in contact with the first interlayer insulating layer. A gate insulating film is provided over the semiconductor layer. A gate electrode is provided over the gate insulating film. At least two first vias are provided in the first interconnect layer and in contact by way of upper ends thereof with the semiconductor layer.

Abstract translation: 公开了一种半导体器件，其在多层互连层中设置有源元件并且在芯片面积上减小。 在第一互连层上提供第二互连层。 第一层间绝缘层设置在第一互连层中。 半导体层设置在第二互连层中并与第一层间绝缘层接触。 在半导体层上设置栅极绝缘膜。 在栅绝缘膜上设置栅电极。 至少两个第一通孔设置在第一互连层中并且通过其上端与半导体层接触。