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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 有权
    半导体器件及其制造方法

    公开(公告)号：US20150056778A1

    公开(公告)日：2015-02-26

    申请号：US14516164

    申请日：2014-10-16

    Applicant: Renesas Electronics Corporation

    Inventor： Kenzo MANABE ,  Naoya INOUE ,  Kenichiro HIJIOKA ,  Yoshihiro HAYASHI

    IPC: H01L27/108 ,  H01L21/768 ,  H01L23/522

    CPC classification number: H01L27/1085 ,  H01L21/768 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.

    Abstract translation: 一种半导体器件，包括：多层布线层，位于基板的上方，其中堆叠由布线和绝缘层构成的多个布线层; 存储电路，其形成在所述基板的存储电路区域中，并且具有嵌入在位于所述多层布线层中的凹部的电容元件; 形成在基板的逻辑电路区域中的逻辑电路; 层叠在由下部电极，电容绝缘膜和上部电极构成的电容元件上的上部耦合布线; 以及形成在构成逻辑电路的布线的上表面上的盖层。 上部连接线的上表面和盖膜的上表面设置在同一平面上。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 有权
    半导体器件及制造半导体器件的方法

    公开(公告)号：US20130092993A1

    公开(公告)日：2013-04-18

    申请号：US13652944

    申请日：2012-10-16

    Applicant: Renesas Electronics Corporation

    Inventor： Kenichiro HIJIOKA ,  Naoya INOUE ,  Yoshihiro HAYASHI

    IPC: H01L29/94 ,  H01L21/02

    CPC classification number: H01L23/528 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10835 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894 ,  H01L28/91 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact.

    Abstract translation: 半导体器件包括衬底，层间绝缘层，第一晶体管，多层互连层，电容器件，金属互连和第一触点。 层间绝缘膜设置在基板上。 将第一晶体管设置在衬底上并埋在层间绝缘层中。 第一晶体管至少具有栅电极和扩散电极。 多层互连层设置在层间绝缘膜的上方。 电容器件设置在多层互连层中。 金属互连与栅电极的上表面接触并埋在层间绝缘层中。 第一触点耦合到第一晶体管的扩散层并且被埋在层间绝缘层中。 金属互连包括与第一接触相同的材料。

    SEMICONDUCTOR DEVICE AND TRANSMISSION-RECEPTION SYSTEM
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND TRANSMISSION-RECEPTION SYSTEM 审中-公开
    半导体器件和传输接收系统

    公开(公告)号：US20160149304A1

    公开(公告)日：2016-05-26

    申请号：US14946509

    申请日：2015-11-19

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kenichiro HIJIOKA ,  Masaaki SODA ,  Masaharu MATSUDAIRA

    IPC: H01Q7/00 ,  H04B1/40

    CPC classification number: H01Q7/00 ,  B41J19/00 ,  H01Q1/38 ,  H04B5/0075

    Abstract: An object of the invention is to transmit a waveform suitable for the reception of signals, while suppressing an increase in man-hours needed for design. A transmission-reception device (2) includes: an antenna element (21) which is terminated at a virtual ground point side of the antenna element by a terminating element (213); a conductor plane (23) which has a predetermined potential and surrounds the antenna element (21); and a transmission circuit (25) that outputs a differential signal to both ends of the antenna element (21). An interval between the conductor plane (23) and a first outer edge (214) of the antenna element (21) is shorter than an interval between the conductor plane (23) and a second outer edge (215) of the antenna element (21).

    Abstract translation: 本发明的目的是在抑制设计所需的工时增加的同时发送适合于接收信号的波形。 发送接收装置（2）包括：天线元件（21），其通过终端元件（213）终止于所述天线元件的虚拟接地点侧; 具有预定电位并围绕天线元件的导体平面（23）; 以及向天线元件（21）的两端输出差分信号的发送电路（25）。 天线元件（21）的导体平面（23）和第一外边缘（214）之间的间隔比天线元件（21）的导体平面（23）和第二外边缘（215）之间的间隔短 ）。

    SKILL TEACHING VERIFICATION SYSTEM AND SKILL TEACHING VERIFICATION PROGRAM
    7.
    发明申请
    SKILL TEACHING VERIFICATION SYSTEM AND SKILL TEACHING VERIFICATION PROGRAM 审中-公开
    技能教学验证系统和技能教学验证程序

    公开(公告)号：US20170061818A1

    公开(公告)日：2017-03-02

    申请号：US15216755

    申请日：2016-07-22

    Applicant: Renesas Electronics Corporation

    Inventor： Kenichiro HIJIOKA ,  Koichi NOSE

    IPC: G09B19/00

    CPC classification number: G09B19/0038 ,  G09B23/28

    Abstract: An object of the present invention is to provide a skill teaching verification system and a skill teaching verification program that can verify an effect of a teaching method for a skill.An analyzing unit analyzes a plurality of pieces of sample data stored in a storing unit using a predetermined multivariate analyzing method. A motion template generation unit generates a standard human body motion model on the basis of an analysis result by the analyzing unit. A motion synthesizing unit generates a corrected human body motion model obtained by correcting the standard human body motion model on the basis of an instruction of a user. A verification unit predicts an attempt result obtained from the corrected human body motion model on the basis of the analysis result by the analyzing unit.

    Abstract translation: 分析单元使用预定的多变量分析方法分析存储在存储单元中的多个样本数据。 运动模板生成单元基于分析单元的分析结果生成标准人体运动模型。 运动合成单元根据用户的指示生成通过校正标准人体运动模型而获得的经校正的人体运动模型。 验证单元基于分析单元的分析结果来预测从校正的人体运动模型获得的尝试结果。

    SEMICONDUCTOR DEVICE WITH CONTACTS AND METAL INTERCONNECTS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE WITH CONTACTS AND METAL INTERCONNECTS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 审中-公开
    具有接触和金属互连的半导体器件及制造半导体器件的方法

    公开(公告)号：US20150371945A1

    公开(公告)日：2015-12-24

    申请号：US14843549

    申请日：2015-09-02

    Applicant: Renesas Electronics Corporation

    Inventor： Kenichiro HIJIOKA ,  Naoya INOUE ,  Yoshihiro HAYASHI

    IPC: H01L23/528 ,  H01L29/94 ,  H01L23/532 ,  H01L27/108

    CPC classification number: H01L23/528 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10835 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894 ,  H01L28/91 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact.

    Abstract translation: 半导体器件包括衬底，层间绝缘层，第一晶体管，多层互连层，电容器件，金属互连和第一触点。 层间绝缘膜设置在基板上。 将第一晶体管设置在衬底上并埋在层间绝缘层中。 第一晶体管至少具有栅电极和扩散电极。 多层互连层设置在层间绝缘膜的上方。 电容器件设置在多层互连层中。 金属互连与栅电极的上表面接触并埋在层间绝缘层中。 第一触点耦合到第一晶体管的扩散层并且被埋在层间绝缘层中。 金属互连包括与第一接触相同的材料。

    WIRELESS COMMUNICATION SYSTEM AND WIRELESS COMMUNICATION APPARATUS
    9.
    发明申请
    WIRELESS COMMUNICATION SYSTEM AND WIRELESS COMMUNICATION APPARATUS 审中-公开
    无线通信系统和无线通信设备

    公开(公告)号：US20140073243A1

    公开(公告)日：2014-03-13

    申请号：US13968281

    申请日：2013-08-15

    Applicant: Renesas Electronics Corporation

    Inventor： Kenichiro HIJIOKA ,  Koichi Yamaguchi ,  Masaharu Matsudaira

    IPC: H04B5/00

    CPC classification number: H04B5/0012 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0093

    Abstract: A first communication device includes a first coupling element and a second communication device includes a second coupling element. The first and second communication devices are configured to wirelessly transmit, between the first and second communication devices, a differential-mode signal and a common-mode signal simultaneously through non-contact coupling between the first and second coupling elements.

    Abstract translation: 第一通信设备包括第一耦合元件，第二通信设备包括第二耦合元件。 第一和第二通信设备被配置为通过第一和第二耦合元件之间的非接触耦合在第一和第二通信设备之间无线地传输差模信号和共模信号。

    SEMICONDUCTOR DEVICE AND COMMUNICATION SYSTEM INCLUDING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND COMMUNICATION SYSTEM INCLUDING THE SAME 有权
    半导体器件和通信系统，包括它们

    公开(公告)号：US20130203361A1

    公开(公告)日：2013-08-08

    申请号：US13739065

    申请日：2013-01-11

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kenichiro HIJIOKA ,  Koichi YAMAGUCHI

    IPC: H04B1/40

    CPC classification number: H04B1/40 ,  H01L23/495 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/73 ,  H01L2223/6677 ,  H01L2224/05553 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: Disclosed is a semiconductor device including a semiconductor chip and a semiconductor package. The semiconductor package includes an antenna formed of a lead frame, a first wire that connects the antenna and a first electrode pad of the semiconductor chip, and a second wire that connects the antenna and a second electrode pad of the semiconductor chip. The semiconductor chip is disposed in one of four regions in the semiconductor package sectioned by line segments connecting midpoints of two pairs of opposing sides of the semiconductor package. A centroid of the semiconductor chip is positioned outside a closed curve composed of a straight line segment connecting a first connection point where the antenna and the first wire are connected and a second connection point where the antenna and the second wire are connected, and a line connecting the first and second connection points along the antenna.

    Abstract translation: 公开了包括半导体芯片和半导体封装的半导体器件。 半导体封装包括由引线框架形成的天线，连接天线的第一导线和半导体芯片的第一电极焊盘以及连接天线和半导体芯片的第二电极焊盘的第二导线。 半导体芯片设置在半导体封装中的四个区域中的一个区域中，该半导体封装通过连接半导体封装的两对相对侧的中点的线段分段。 半导体芯片的质心位于由连接天线和第一线连接的第一连接点的直线段和连接天线和第二线的第二连接点组成的闭合曲线之外，线 沿着天线连接第一和第二连接点。

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