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公开(公告)号：US20150311706A1
公开(公告)日：2015-10-29
申请号：US14690381
申请日：2015-04-18
Applicant: Renesas Electronics Corporation
Inventor： Koichiro NOGUCHI , Koichi NOSE , Yoshifumi IKENAGA , Yoichi YOSHIDA
Abstract: A power supply device according to an embodiment comprises a plurality of power sources 10 each including an antenna and an AC/DC conversion unit, a plurality of consolidating units 13—1 to 13—i, and a power supply unit 15. The consolidating units 13—1 to 13—i respectively include consolidating circuits 14—1 to 14—i that selectively consolidate a plurality of DC signals 21—1 to 21—n supplied by the plurality of power sources 10. The power supply unit 15 includes a consolidating circuit 16 that selectively consolidates the DC signals 21—1 to 21—i output from the plurality of consolidating units 13—1 to 13—i, and a voltage conversion circuit 17 that converts a DC signal 23 resulting from consolidation in the consolidating circuit 16, to a predetermined voltage.
Abstract translation: 根据实施例的电源装置包括多个电源10，每个电源10包括天线和AC / DC转换单元，多个合并单元13-1至13-i和电源单元15.合并单元 13-1至13-i分别包括选择性地合并由多个电源10提供的多个DC信号21-1至21-n的合并电路14-1至14-i。电源单元15包括合并 电路16，其选择性地合并从多个合并单元13-1至13-i输出的DC信号21-1至21-i;以及电压转换电路17，其将由巩固电路16中的合并产生的DC信号23转换 ，达到预定电压。
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公开(公告)号：US20180323779A1
公开(公告)日：2018-11-08
申请号：US16024097
申请日：2018-06-29
Applicant: Renesas Electronics Corporation
Inventor： Koichiro NOGUCHI , Koichi NOSE , Yoshifumi IKENAGA , Yoichi YOSHIDA
IPC: H03K17/16
CPC classification number: H03K17/162 , H02M1/36 , H02M3/07 , H02M3/155 , H03K17/0814
Abstract: According to one embodiment, a semiconductor device includes: a first switch SWx which switches whether or not to supply a first power supply voltage Vx generated by accumulating a charge outputted from a power source 10, as a second power supply voltage VDD to a first circuit 13, and a second switch SW1 which switches whether or not to connect to the first circuit 13 a smoothing capacitor C1 which suppresses a fluctuation of the second power supply voltage VDD, and the first switch SWx is switched to an on state in response to that the first power supply voltage Vx has reached a sufficient voltage, and then the second switch SW1 is switched to the on state in response to that the second power supply voltage VDD has reached a sufficient voltage.
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公开(公告)号：US20210132866A1
公开(公告)日：2021-05-06
申请号：US17090534
申请日：2020-11-05
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Shunsuke OKUMURA , Koichi NOSE
Abstract: A data processing device includes: an input data determining unit configured to determine whether or not each of binarized input data is a predetermined value; a storage unit configured to store a plurality of coefficients and coefficient address information including information related to coefficient addresses where the plurality of coefficients are stored; a control unit configured to read the coefficient address from the storage unit based on a determination result of the input data determining unit and read the coefficient from the storage unit based on the coefficient address; and an arithmetic unit configured to execute an arithmetic operation related to the coefficient acquired by the control unit.
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公开(公告)号：US20170300329A1
公开(公告)日：2017-10-19
申请号：US15513544
申请日：2014-11-11
Applicant: Renesas Electronics Corporation
Inventor： Koichiro NOGUCHI , Osamu OKAZAKI , Shunichi KAERIYAMA , Koichi NOSE
CPC classification number: G06F9/30076 , G06F9/30087 , G06F9/38 , G06F9/3836 , G06F9/52
Abstract: An instruction execution control system includes a plurality of instruction storage units configured to output instructions in an FIFO order to a plurality of instruction execution units configured to execute the instructions; an instruction control unit configured to assign each of a plurality of the sequentially input instructions to one of the instruction storage units, and an output control unit configured to control the output of the instructions from the instruction storage units. When the input instruction is a dummy instruction to be inserted between instructions that should be executed in an execution order, the instruction control unit distributes the input instruction to the plurality of instruction storage units. The output control unit stops the output of the instructions from the instruction storage unit, the instruction output therefrom has become the dummy instruction, to the instruction execution unit until instructions output from all instruction storage units become the dummy instructions.
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公开(公告)号：US20180083494A1
公开(公告)日：2018-03-22
申请号：US15826062
申请日：2017-11-29
Applicant: Renesas Electronics Corporation
Inventor： Koichiro NOGUCHI , Koichi NOSE , Yoshifumi IKENAGA , Yoichi YOSHIDA
Abstract: A power supply device includes a plurality of power sources each including an antenna and an AC/DC conversion unit that converts an AC signal received by the antenna to a DC signal, a plurality of consolidating units each including a first consolidating circuit that selectively consolidates a plurality of DC signals supplied by the plurality of power sources, and a power supply unit that includes a second consolidating circuit that selectively consolidates DC signals output from the plurality of consolidating units, and a first voltage conversion circuit that converts a DC signal resulting from consolidation in the second consolidating circuit, to a predetermined voltage.
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Patent Agency Ranking
公开(公告)号：US20170171408A1
公开(公告)日：2017-06-15
申请号：US15358311
申请日：2016-11-22
Applicant: Renesas Electronics Corporation
Inventor： Kenichiro HIJIOKA , Koichi NOSE , Shunsuke OKUMURA
CPC classification number: H04N1/00795 , H04N1/3876 , H04N2201/0081 , H04N2201/0096 , H04N2201/0424 , H04N2201/0426 , H04N2201/0434
Abstract: A scanning system 9 according to the present invention includes an image acquisition unit 91 that acquires a plurality of pieces of image information generated by continuously scanning a medium to be scanned, a path calculation unit 92 that calculates a path of scanning the medium based on the plurality of pieces of image information acquired by the image acquisition unit 91, a processing method determination unit 93 that determines a processing method of the plurality of pieces of image information in accordance with a path calculated by the path calculation unit 92, and a processing unit 94 that processes the plurality of pieces of image information by a processing method determined by the processing method determination unit 93 and converts the plurality of pieces of image information into information in a form corresponding to the processing method.
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7.发明申请公开(公告)号：US20170061818A1
公开(公告)日：2017-03-02
申请号：US15216755
申请日：2016-07-22
Applicant: Renesas Electronics Corporation
Inventor： Kenichiro HIJIOKA , Koichi NOSE
IPC: G09B19/00
CPC classification number: G09B19/0038 , G09B23/28
Abstract: An object of the present invention is to provide a skill teaching verification system and a skill teaching verification program that can verify an effect of a teaching method for a skill.An analyzing unit analyzes a plurality of pieces of sample data stored in a storing unit using a predetermined multivariate analyzing method. A motion template generation unit generates a standard human body motion model on the basis of an analysis result by the analyzing unit. A motion synthesizing unit generates a corrected human body motion model obtained by correcting the standard human body motion model on the basis of an instruction of a user. A verification unit predicts an attempt result obtained from the corrected human body motion model on the basis of the analysis result by the analyzing unit.
Abstract translation: 分析单元使用预定的多变量分析方法分析存储在存储单元中的多个样本数据。 运动模板生成单元基于分析单元的分析结果生成标准人体运动模型。 运动合成单元根据用户的指示生成通过校正标准人体运动模型而获得的经校正的人体运动模型。 验证单元基于分析单元的分析结果来预测从校正的人体运动模型获得的尝试结果。
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公开(公告)号：US20230008014A1
公开(公告)日：2023-01-12
申请号：US17369686
申请日：2021-07-07
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Shunsuke OKUMURA , Koichi NOSE
Abstract: The data processing device includes the inference processor and learning processor. The inference processor includes a input data determination circuit for determining whether or not each of the binarized input data is a predetermined value, a memory for storing a plurality of coefficient and a coefficient address information including information about a coefficient address in which a plurality of coefficient are stored, an inference controller for reading coefficient address from the storage unit based on a determination result of the input data determination circuit and reading coefficient from the storage unit based on coefficient address, a arithmetic circuit for performing an operation using the binarized input data and coefficient acquired by the inference controller to generate the arithmetic operation result as a output data.
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公开(公告)号：US20170310236A1
公开(公告)日：2017-10-26
申请号：US15646582
申请日：2017-07-11
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Shunichi KAERIYAMA , Kouichi YAMAGUCHI , Koichi NOSE
CPC classification number: H04B5/0031 , H01L2224/451 , H01L2224/48137 , H01L2924/12032 , H01L2924/13091 , H04B3/50 , H04L25/0266 , H04L25/4902 , H01L2924/00 , H01L2924/00014
Abstract: Provided is a receiving circuit that operates in a power supply system different from a transmitting circuit outputting a transmission signal and receives the transmission signal through an AC coupling device where a primary coil through which the transmission signal flows and a secondary coil having a center tap to which a specified voltage is supplied from an external terminal are magnetically coupled, which includes a pulse width amplifier circuit that holds pulse signals appearing at both ends of the secondary coil for a specified period of time and outputs them as hold signals, respectively, and a differential amplifier that compares a voltage of the hold signal and a voltage of the hold signal and outputs a comparison result.
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公开(公告)号：US20170185836A1
公开(公告)日：2017-06-29
申请号：US15383304
申请日：2016-12-19
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Shunsuke OKUMURA , Koichi NOSE , Kenichiro HIJIOKA
CPC classification number: G06K9/00483 , G06K9/00181 , G06K9/00187 , G06K9/24 , G06K9/6215 , G06K9/66 , G06T7/70 , G06T2207/30204 , H04N1/107 , H04N2201/0081 , H04N2201/0096 , H04N2201/0434 , H04N2201/3245
Abstract: A marking analysis system includes a marking data storage unit to store a plurality of marking data indicating a plurality of positions marked by a user in a book so as to correspond respectively to a plurality of users, a marking distribution analysis unit that analyzes the marking data and calculates a marking frequency for each of a plurality of unit areas in the book, and generates marking distribution characteristic data indicating a distribution of the marking frequency with respect to a position in the unit area, a marking distribution characteristic data storage unit to store the marking distribution characteristic data, and a similar user retrieval unit that, when determining that the distribution of the marking frequency indicated by the marking distribution characteristic data of a target user selected as a processing target and the distribution of the marking frequency indicated by the marking distribution characteristic data of another user are similar, extracts the another user as a similar user who is similar to the target user.
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