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    Small loop delay clock and data recovery block for high-speed next generation C-PHY
    1.
    发明授权
    Small loop delay clock and data recovery block for high-speed next generation C-PHY 有权

    公开(公告)号：US11095425B2

    公开(公告)日：2021-08-17

    申请号：US17001801

    申请日：2020-08-25

    Applicant: QUALCOMM Incorporated

    Inventor： Ying Duan ,  Jing Wu ,  Shih-Wei Chou

    IPC: H04B3/00 ,  H04L25/00 ,  H04L7/00

    Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.

    Uniform predicates in shaders for graphics processing units
    3.
    发明授权
    Uniform predicates in shaders for graphics processing units 有权

    公开(公告)号：US10115175B2

    公开(公告)日：2018-10-30

    申请号：US15048599

    申请日：2016-02-19

    Applicant: QUALCOMM Incorporated

    Inventor： Andrew Evan Gruber ,  Pramod Vasant Argade ,  Jing Wu

    IPC: G06T1/20 ,  G06T5/00 ,  G06F9/30 ,  G06F9/38

    Abstract: A method for processing data in a graphics processing unit including receiving an indication that all threads of a warp in a graphics processing unit (GPU) are to execute a same branch in a first set of instructions, storing one or more predicate bits in a memory as a single set of predicate bits, wherein the single set of predicate bits applies to all of the threads in the warp, and executing a portion of the first set of instructions in accordance with the single set of predicate bits. Executing the first set of instructions may include executing the first set of instruction in accordance with the single set of predicate bits using a single instruction, multiple data (SIMD) processing core and/or executing the first set of instruction in accordance with the single set of predicate bits using a scalar processing unit.

    C-PHY half-rate clock and data recovery adaptive edge tracking
    4.
    发明授权
    C-PHY half-rate clock and data recovery adaptive edge tracking 有权

    公开(公告)号：US10033519B2

    公开(公告)日：2018-07-24

    申请号：US15348290

    申请日：2016-11-10

    Applicant: QUALCOMM Incorporated

    Inventor： Ying Duan ,  Yasser Ahmed ,  Abhay Dixit ,  Harry Huy Dang ,  Jing Wu

    IPC: H04L29/06 ,  H04L7/00

    Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where each pair of symbols includes a first symbol and a second symbol, generating a second clock signal by delaying the first clock signal by a first delay value, generating a third clock signal by delaying the second clock signal, calibrating the second clock signal and the third clock signal by initializing the first delay value such that the first sampling circuit, the second sampling circuit and the third sampling circuit capture the same symbol in a first pair of symbols, and incrementally increasing the first delay value until the second sampling circuit and the third sampling circuit capture different symbols from each pair of symbols.

    GENERAL PURPOSE REGISTER ALLOCATION IN STREAMING PROCESSOR
    5.
    发明申请
    GENERAL PURPOSE REGISTER ALLOCATION IN STREAMING PROCESSOR 审中-公开

    公开(公告)号：US20180165092A1

    公开(公告)日：2018-06-14

    申请号：US15379195

    申请日：2016-12-14

    Applicant: QUALCOMM Incorporated

    Inventor： Yun Du ,  Liang Han ,  Lin Chen ,  Chihong Zhang ,  Hongjiang Shang ,  Jing Wu ,  Zilin Ying ,  Chun Yu ,  Guofang Jiao ,  Andrew Gruber ,  Eric Demers

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Systems and techniques are disclosed for general purpose register dynamic allocation based on latency associated with of instructions in processor threads. A streaming processor can include a general purpose registers configured to stored data associated with threads, and a thread scheduler configured to receive allocation information for the general purpose registers, the information describing general purpose registers that are to be assigned as persistent general purpose registers (pGPRs) and volatile general purpose registers (vGPRs). The plurality of general purpose registers can be allocated according to the received information. The streaming processor can include the general purpose registers allocated according to the received information, the allocated based on execution latencies of instructions included in the threads.

    UNIFORM PREDICATES IN SHADERS FOR GRAPHICS PROCESSING UNITS
    6.
    发明申请
    UNIFORM PREDICATES IN SHADERS FOR GRAPHICS PROCESSING UNITS 审中-公开

    公开(公告)号：US20170243320A1

    公开(公告)日：2017-08-24

    申请号：US15048599

    申请日：2016-02-19

    Applicant: QUALCOMM Incorporated

    Inventor： Andrew Evan Gruber ,  Pramod Vasant Argade ,  Jing Wu

    IPC: G06T1/20 ,  G06T5/00

    CPC classification number: G06T1/20 ,  G06F9/30072 ,  G06F9/3851 ,  G06F9/3887 ,  G06T5/008

    Abstract: A method for processing data in a graphics processing unit including receiving an indication that all threads of a warp in a graphics processing unit (GPU) are to execute a same branch in a first set of instructions, storing one or more predicate bits in a memory as a single set of predicate bits, wherein the single set of predicate bits applies to all of the threads in the warp, and executing a portion of the first set of instructions in accordance with the single set of predicate bits. Executing the first set of instructions may include executing the first set of instruction in accordance with the single set of predicate bits using a single instruction, multiple data (SIMD) processing core and/or executing the first set of instruction in accordance with the single set of predicate bits using a scalar processing unit.

    Frequency doubler based on phase frequency detectors using rising edge delay
    7.
    发明授权
    Frequency doubler based on phase frequency detectors using rising edge delay 有权

    公开(公告)号：US10944386B1

    公开(公告)日：2021-03-09

    申请号：US16928218

    申请日：2020-07-14

    Applicant: QUALCOMM Incorporated

    Inventor： Jing Wu ,  Ying Duan ,  Zhi Zhu

    IPC: H03K5/00 ,  H03K5/135 ,  H03B19/14

    Abstract: Certain aspects of the present disclosure generally relate to techniques and apparatus for doubling the frequency of a signal. For example, certain aspects are directed to a phase frequency detector (PFD)-based rising-edge-delay-only frequency doubling circuit. One example frequency doubler circuit generally includes a first delay stage, a second delay stage, a first PFD, a first rising-edge-only adjustable delay cell, a second PFD, a second rising-edge-only adjustable delay cell a logic gate, and a comparator configured to compare a direct-current (DC) voltage value of an output of the logic gate with a reference voltage and control the first and second rising-edge-only adjustable delay cells based on the comparison.

    C-PHY HALF-RATE CLOCK AND DATA RECOVERY ADAPTIVE EDGE TRACKING
    8.
    发明申请
    C-PHY HALF-RATE CLOCK AND DATA RECOVERY ADAPTIVE EDGE TRACKING 审中-公开

    公开(公告)号：US20180131503A1

    公开(公告)日：2018-05-10

    申请号：US15348290

    申请日：2016-11-10

    Applicant: QUALCOMM Incorporated

    Inventor： Ying Duan ,  Yasser Ahmed ,  Abhay Dixit ,  Harry Huy Dang ,  Jing Wu

    IPC: H04L7/00 ,  H04L29/06

    CPC classification number: H04L7/0012 ,  G06F13/40 ,  G06F13/4291 ,  H04L7/0004 ,  H04L7/0037 ,  H04L7/0337 ,  H04L25/14 ,  H04L25/49 ,  H04L69/28

    Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where each pair of symbols includes a first symbol and a second symbol, generating a second clock signal by delaying the first clock signal by a first delay value, generating a third clock signal by delaying the second clock signal, calibrating the second clock signal and the third clock signal by initializing the first delay value such that the first sampling circuit, the second sampling circuit and the third sampling circuit capture the same symbol in a first pair of symbols, and incrementally increasing the first delay value until the second sampling circuit and the third sampling circuit capture different symbols from each pair of symbols.

    Small loop delay clock and data recovery block for high-speed next generation C-PHY
    10.
    发明授权
    Small loop delay clock and data recovery block for high-speed next generation C-PHY 有权

    公开(公告)号：US11411711B2

    公开(公告)日：2022-08-09

    申请号：US17305542

    申请日：2021-07-09

    Applicant: QUALCOMM Incorporated

    Inventor： Ying Duan ,  Jing Wu ,  Shih-Wei Chou

    IPC: H04B3/00 ,  H04L25/00 ,  H04L7/00

    Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.

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