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公开(公告)号：US20190050958A1
公开(公告)日：2019-02-14
申请号：US16103336
申请日：2018-08-14
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Pramod Vasant Argade , Jing Wu
Abstract: A method for processing data in a graphics processing unit including receiving an indication that all threads of a warp in a graphics processing unit (GPU) are to execute a same branch in a first set of instructions, storing one or more predicate bits in a memory as a single set of predicate bits, wherein the single set of predicate bits applies to all of the threads in the warp, and executing a portion of the first set of instructions in accordance with the single set of predicate bits. Executing the first set of instructions may include executing the first set of instruction in accordance with the single set of predicate bits using a single instruction, multiple data (SIMD) processing core and/or executing the first set of instruction in accordance with the single set of predicate bits using a scalar processing unit.
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公开(公告)号：US20160048374A1
公开(公告)日：2016-02-18
申请号：US14461890
申请日：2014-08-18
Applicant: QUALCOMM Incorporated
Inventor： Pramod Vasant Argade , Andrew Evan Gruber , Chiente Ho , Stewart Griffin Hall , Lin Chen
CPC classification number: G06F7/5443 , G06F5/01 , G06F7/483 , G06F7/57
Abstract: At least one processor may emulate a fused multiply-add operation for a first operand, a second operand, and a third operand. The at least one processor may determine an intermediate value based at least in part on multiplying the first operand with the second operand, determine at least one of an upper intermediate value or a lower intermediate value, wherein determining the upper intermediate value comprises rounding, towards zero, the intermediate value by a specified number of bits, and wherein determining the lower intermediate value comprises subtracting the intermediate value by the upper intermediate value, determine an upper value and a lower value based at least in part on adding or subtracting the third operand to one of the upper intermediate value or the lower intermediate value, and determine an emulated fused multiply-add result by adding the upper value and the lower value.
Abstract translation: 至少一个处理器可以模拟第一操作数，第二操作数和第三操作数的融合乘法运算。 至少一个处理器可以至少部分地基于将第一操作数与第二操作数相乘来确定中间值，确定上中间值或下中间值中的至少一个，其中确定上中间值包括四舍五入 零，中间值乘以指定位数，并且其中确定较低中间值包括通过上述中间值减去中间值，至少部分地基于加上或减去第三操作数来确定上限值和较低值 到较高中间值或较低中间值之一，并通过加上上限值和下限值来确定仿真融合乘法运算结果。
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Patent Agency Ranking
公开(公告)号：US20160019027A1
公开(公告)日：2016-01-21
申请号：US14331991
申请日：2014-07-15
Applicant: QUALCOMM Incorporated
Inventor： Lin Chen , Andrew Evan Gruber , Guofang Jiao , Chiente Ho , Pramod Vasant Argade
IPC: G06F5/01
CPC classification number: G06F7/49936 , G06F7/552 , G06F2207/5525 , G09C1/00 , H04L2209/12
Abstract: At least one processor may receive components of a vector, wherein each of the components of the vector comprises at least an exponent. The at least one processor may further determine a maximum exponent out of respective exponents of the components of the vector, and may determine a scaling value based at least in part on the maximum exponent. An arithmetic logic unit of the at least one processor may scale the vector, by subtracting the scaling value from each of the respective exponents of the components of the vector.
Abstract translation: 至少一个处理器可以接收向量的分量，其中矢量的每个分量包括至少一个指数。 所述至少一个处理器可以进一步确定向量的分量的相应指数中的最大指数，并且可以至少部分地基于最大指数来确定缩放值。 所述至少一个处理器的算术逻辑单元可以通过从所述矢量的各个成分的各指数中减去所述缩放值来缩放所述向量。
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公开(公告)号：US10115175B2
公开(公告)日：2018-10-30
申请号：US15048599
申请日：2016-02-19
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Pramod Vasant Argade , Jing Wu
Abstract: A method for processing data in a graphics processing unit including receiving an indication that all threads of a warp in a graphics processing unit (GPU) are to execute a same branch in a first set of instructions, storing one or more predicate bits in a memory as a single set of predicate bits, wherein the single set of predicate bits applies to all of the threads in the warp, and executing a portion of the first set of instructions in accordance with the single set of predicate bits. Executing the first set of instructions may include executing the first set of instruction in accordance with the single set of predicate bits using a single instruction, multiple data (SIMD) processing core and/or executing the first set of instruction in accordance with the single set of predicate bits using a scalar processing unit.
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公开(公告)号：US20170243320A1
公开(公告)日：2017-08-24
申请号：US15048599
申请日：2016-02-19
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Pramod Vasant Argade , Jing Wu
CPC classification number: G06T1/20 , G06F9/30072 , G06F9/3851 , G06F9/3887 , G06T5/008
Abstract: A method for processing data in a graphics processing unit including receiving an indication that all threads of a warp in a graphics processing unit (GPU) are to execute a same branch in a first set of instructions, storing one or more predicate bits in a memory as a single set of predicate bits, wherein the single set of predicate bits applies to all of the threads in the warp, and executing a portion of the first set of instructions in accordance with the single set of predicate bits. Executing the first set of instructions may include executing the first set of instruction in accordance with the single set of predicate bits using a single instruction, multiple data (SIMD) processing core and/or executing the first set of instruction in accordance with the single set of predicate bits using a scalar processing unit.
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公开(公告)号：US09645792B2
公开(公告)日：2017-05-09
申请号：US14461890
申请日：2014-08-18
Applicant: QUALCOMM Incorporated
Inventor： Pramod Vasant Argade , Andrew Evan Gruber , Chiente Ho , Stewart Griffin Hall , Lin Chen
CPC classification number: G06F7/5443 , G06F5/01 , G06F7/483 , G06F7/57
Abstract: At least one processor may emulate a fused multiply-add operation for a first operand, a second operand, and a third operand. The at least one processor may determine an intermediate value based at least in part on multiplying the first operand with the second operand, determine at least one of an upper intermediate value or a lower intermediate value, wherein determining the upper intermediate value comprises rounding, towards zero, the intermediate value by a specified number of bits, and wherein determining the lower intermediate value comprises subtracting the intermediate value by the upper intermediate value, determine an upper value and a lower value based at least in part on adding or subtracting the third operand to one of the upper intermediate value or the lower intermediate value, and determine an emulated fused multiply-add result by adding the upper value and the lower value.
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公开(公告)号：US10706494B2
公开(公告)日：2020-07-07
申请号：US16103336
申请日：2018-08-14
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Pramod Vasant Argade , Jing Wu
Abstract: A method for processing data in a graphics processing unit including receiving an indication that all threads of a warp in a graphics processing unit (GPU) are to execute a same branch in a first set of instructions, storing one or more predicate bits in a memory as a single set of predicate bits, wherein the single set of predicate bits applies to all of the threads in the warp, and executing a portion of the first set of instructions in accordance with the single set of predicate bits. Executing the first set of instructions may include executing the first set of instruction in accordance with the single set of predicate bits using a single instruction, multiple data (SIMD) processing core and/or executing the first set of instruction in accordance with the single set of predicate bits using a scalar processing unit.
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