公开(公告)号：US06370191B1

公开(公告)日：2002-04-09

申请号：US09431687

申请日：1999-11-01

申请人： Shivaling S. Mahant-Shetti ,  Srinath Hosur ,  Alan Gatherer

发明人： Shivaling S. Mahant-Shetti ,  Srinath Hosur ,  Alan Gatherer

IPC分类号： H04L2710

CPC分类号： G06F7/552 ,  G06F2207/5525 ,  H04L25/0307 ,  H04L2025/03401 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03573 ,  H04L2025/0363

摘要： A cable modem (20) having a blind equalizer (40) in its equalization function (28) is disclosed. The blind equalizer (40) includes an adaptive equalizer (44) and an approximating update function (42) that provides updated equalization coefficients to the adaptive equalizer (44) using the Constant Modulus Algorithm, wherein the error in the adaptive equalizer output is estimated. The estimates are based upon a determination of the maximum and minimum of the real and i components of symbols output by the adaptive equalizer (44). Efficiency in the computations required for updating the equalizer coefficients is obtained, without sacrificing convergence.

摘要翻译： 公开了一种在其均衡功能（28）中具有盲均衡器（40）的电缆调制解调器（20）。 盲均衡器（40）包括使用恒模算法向自适应均衡器（44）提供更新的均衡系数的自适应均衡器（44）和近似更新功能（42），其中估计自适应均衡器输出中的误差。 估计基于由自适应均衡器（44）输出的符号的真实和i分量的最大值和最小值的确定。 获得更新均衡器系数所需的计算的效率，而不会牺牲收敛。

公开(公告)号：US4736334A

公开(公告)日：1988-04-05

申请号：US791700

申请日：1985-10-28

申请人： Soenke Mehrgardt

发明人： Soenke Mehrgardt

IPC分类号： G06F17/10 ,  G06F7/552 ,  G06F17/16

CPC分类号： G06F7/552 ,  G06F2207/5525

摘要： The circuit arrangement includes a basic circuit for calculating the zeroth approximation and expandable by at least one correction circuit for calculating a first or further approximations. The basic circuit contains a first adder, a second adder, a first constant multiplier, a second constant multiplier, a first absolute-value stage, a second absolute-value stage and a third absolute-value stage which is interposed between a subtracter and the input of the second constant multiplier. The output of the second constant multiplier is coupled to one input of the second adder, whose output provides the zeroth approximation to the value of the complex digital quantity. Each of the two input signals is fed through one of the absolute-value stages to one of the two inputs of the subtracter and the first adder.

摘要翻译： 该电路装置包括用于计算第零近似值并由至少一个用于计算第一或其它近似值的校正电路展开的基本电路。 基本电路包括第一加法器，第二加法器，第一常数乘法器，第二常数乘法器，第一绝对值级，第二绝对值级和第三绝对值级，其介于减法器与第 输入第二个常数乘数。 第二常数乘法器的输出耦合到第二加法器的一个输入，其输出提供对复数数字量的值的第零近似。 两个输入信号中的每一个通过绝对值级中的一个馈送到减法器和第一加法器的两个输入中的一个。

公开(公告)号：US4692889A

公开(公告)日：1987-09-08

申请号：US655657

申请日：1984-09-28

申请人： David L. McNeely

发明人： David L. McNeely

IPC分类号： H04N9/64 ,  G06F1/035 ,  G06F7/48 ,  G06F7/552 ,  G06F7/556

CPC分类号： G06F7/552 ,  G06F1/0356 ,  G06F7/4806 ,  G06F2101/08 ,  G06F2207/5525

摘要： An arrangement is provided for computing the magnitude value of the vector sum of two quadrature-related component signals I and Q with a minimal of hardware. To this end, the magnitude values of the orthogonal I and Q signals are applied to a ROM as address codes to produce the Log.sub.B .vertline.I.vertline. and Log.sub.B .vertline.Q.vertline. values to the logarithmic base B. The smaller of the Log.sub.B .vertline.I.vertline. and Log.sub.B .vertline.Q.vertline. logarithmic values is subtracted from the larger of the logarithmic values to produce the absolute value .vertline.D.vertline. of the difference between the respective logarithmic values. The difference value D is applied to a ROM as an address code which is programmed to generate a correction value F=0.5 Log.sub.B (1+B.sup.-2.vertline.D.vertline.). The correction value F is added to the larger of the two logarithmic values, and the antilog of the sum is computed to determine the magnitude value C of the vector sum of the two quadrature signals I and Q.

摘要翻译： 提供了一种用于以最小的硬件来计算两个正交相关分量信号I和Q的矢量和的幅度值的装置。 为此，将正交I和Q信号的幅度值作为地址代码施加到ROM，以产生LogB | I |和LogB | Q |值到对数基数B. LogB | I|和 从较大的对数值中减去LogB | Q对数值，以产生相应对数值之差的绝对值| D |。 差分值D作为编程为产生校正值F = 0.5LogB（1 + B-2|D|）的地址码的ROM被应用于ROM。 校正值F被加到两个对数值中的较大者中，并且计算和的反序号以确定两个正交信号I和Q的向量和的幅度值C.

公开(公告)号：US3829671A

公开(公告)日：1974-08-13

申请号：US35462173

申请日：1973-04-25

申请人： WESTINGHOUSE ELECTRIC CORP

发明人： GATHRIGHT J ,  PARK R

IPC分类号： G06F7/544 ,  G06F7/552 ,  G06F7/38

CPC分类号： G06F7/552 ,  G06F7/544 ,  G06F2207/5525

摘要： An arithmetic logic circuit for performing an algorithm which approximates the square root of the sum of two squares. A novel hardware arrangement and method are disclosed which employ EXCLUSIVE OR circuits instead of a conventional 2''s complement arrangement provided by conventional adder-subtractor circuits. The values to be squared are converted to positive value digital signals, compared, and the control signal from a comparison circuit used to command the full value of the larger digital signal and half the value of the smaller digital signal into an adder circuit which receives a correction signal in the event either of the input digital values is negative. The correction signal may be added to the least significant order of the adder output signal or to the next to least significant order depending upon whether the larger or smaller of the digital signals is negative.

公开(公告)号：US07693921B2

公开(公告)日：2010-04-06

申请号：US11161843

申请日：2005-08-18

申请人： Chanaveeragouda V Goudar

发明人： Chanaveeragouda V Goudar

IPC分类号： G06F7/00

CPC分类号： G10L15/10 ,  G06F7/552 ,  G06F2207/5525

摘要： An aspect of the present invention takes advantage of the fact that the coordinates of fixed points do not change, and thus the energy (sum of squares of the coordinates defining the vector) of each fixed point is computed and stored. The energy of each variable input point may also be computed. The distance between each pair of fixed and input points is computed based on the respective energies and the dot product.

摘要翻译： 本发明的一个方面利用固定点的坐标不变的事实，因此计算并存储每个固定点的能量（定义矢量的坐标的平方和）。 也可以计算每个可变输入点的能量。 基于相应的能量和点积来计算每对固定点和输入点之间的距离。

公开(公告)号：US6070181A

公开(公告)日：2000-05-30

申请号：US49605

申请日：1998-03-27

申请人： Scott Yeh

发明人： Scott Yeh

IPC分类号： G06F7/552

CPC分类号： G06F7/552 ,  G06F2207/5525

摘要： An envelope detection method by using a peel cone approximation concept and an envelope detection circuit which implements the envelope detection method are disclosed. The envelope detection circuit includes an absolute value-determining circuit, a maximum/minimum value-determining circuit, a plurality sets of comparison circuits, an address encoder, a read only memory (ROM), and a multiplier/adder. A delaying circuit for synchronization is further included in the envelope detection circuit. With the method and the circuit for an envelope detection by using a peel cone approximation, advantages of a compact circuit structure, less operation latency, a low approximation error and a low cost are all achieved.

摘要翻译： 公开了一种通过使用剥离锥近似概念的包络检测方法和实现包络检测方法的包络检测电路。 包络检测电路包括绝对值确定电路，最大/最小值确定电路，多组比较电路，地址编码器，只读存储器（ROM）和乘法器/加法器。 用于同步的延迟电路还包括在包络检测电路中。 通过使用剥离锥近似的用于包络检测的方法和电路，可以实现紧凑的电路结构，较少的操作延迟，低近似误差和低成本的优点。

公开(公告)号：US5862068A

公开(公告)日：1999-01-19

申请号：US850820

申请日：1997-05-02

申请人： Takashi Onodera

发明人： Takashi Onodera

IPC分类号： G06F7/00 ,  G06F7/552 ,  G06F7/76 ,  G06F17/10 ,  H03F3/45 ,  G06F7/38

CPC分类号： G06F7/552 ,  G06F2207/5525 ,  G06F7/49942

摘要： An arithmetic circuit with a small number of parts performs high-speed arithmetic operations for calculating a square-root of a sum of squares of two numbers. Absolute values of two inputs S.sub.in1 and S.sub.in2 are determined by absolute value calculators and are compared by an absolute value comparator According to the comparison result, a first multiplexer selects the smaller of the two absolute values and a second multiplexer selects the larger of the two absolute values. The smaller absolute value is shifted by a 2-bit right shifter and by a 3-bit right shifter respectively, and the obtained shifted results are added together by a (N-2)-bit adder. The sum of the shifted values is then added by a N-bit adder to the larger absolute value. A square-root of the square-sum of two inputs S.sub.in1 and S.sub.in2 is thus approximately determined,

摘要翻译： 具有少量部件的算术电路执行用于计算两个数字的平方和的平方根的高速算术运算。 两个输入Sin1和Sin2的绝对值由绝对值计算器确定，并通过绝对值比较器进行比较根据比较结果，第一个多路复用器选择两个绝对值中较小的一个，第二个多路复用器选择两个绝对值中较大的绝对值 价值观。 较小的绝对值分别由2位右移位器和3位右移位器移位，并将获得的移位结果通过（N-2）位加法器相加在一起。 移位值的和然后由N位加法器加到较大的绝对值。 因此，近似地确定两个输入Sin1和Sin2的平方和的平方根，

公开(公告)号：US5650953A

公开(公告)日：1997-07-22

申请号：US468186

申请日：1995-06-06

申请人： Takashi Kaku ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Hideo Miyazawa

IPC分类号： H04L27/00 ,  G06F7/48 ,  G06F7/552 ,  G06F17/10 ,  H04M11/00

CPC分类号： G06F7/5525 ,  G06F17/10 ,  G06F7/4806 ,  G06F7/552 ,  G06F2207/5521 ,  G06F2207/5525

摘要： The level of the input vector signal (X+jY) is reduced to (X+jY)/.sqroot.2 in the overflow preventing circuit. A power arithmetic operating circuit squares the level-down input vector signal, to obtain a power value (X.sup.2 +Y.sup.2)/2. The initial value of the tap value (K) which is finally set to a reciprocal number value is multiplied two times by a multiplying circuit, thereby obtaining K.sup.2 (X+Y).sup.2 /2. Further, a differential circuit obtains an error signal (.DELTA.K)=1/2-K.sup.2 (X.sup.2 +Y.sup.2)/2 with a reference. An updating circuit updates the tap value (K) so that the error signal (.DELTA.K) is equal to 0. A loop arithmetic operation of the multiplication of the tap value, differential arithmetic operation, and updating of the tap value is repeated until the error signal (.DELTA.K) is converged to a predetermined value or less. The tap value (K) when it was converged is obtained as a reciprocal number value 1/.sqroot.(X.sup.2 +Y.sup.2) of the amplitude of the input vector signal.

摘要翻译： 在溢出防止电路中，输入矢量信号（X + jY）的电平减小到（X + jY）/ 2ROOT2。 功率算术运算电路使电平降低输入矢量信号平方，以获得功率值（X2 + Y2）/ 2。 将最终设定为倒数的抽头值（K）的初始值乘以乘法电路两次，从而得到K2（X + Y）2/2。 此外，差分电路获得参考的误差信号（DELTA K）= 1/2-K2（X2 + Y2）/ 2。 更新电路更新抽头值（K），使得误差信号（DELTA K）等于0.重复抽头值，微分算术运算和抽头值的更新的相乘的循环算术运算，直到 误差信号（DELTA K）收敛到预定值或更小。 获得收敛时的抽头值（K）作为输入矢量信号的幅度的倒数值1 / 2ROOT（X2 + Y2）。

公开(公告)号：US20090326932A1

公开(公告)日：2009-12-31

申请号：US12555242

申请日：2009-09-08

申请人： Chanaveeragouda V. Goudar

发明人： Chanaveeragouda V. Goudar

IPC分类号： G10L19/12

CPC分类号： G10L15/10 ,  G06F7/552 ,  G06F2207/5525

摘要： An aspect of the present invention takes advantage of the fact that the coordinates of fixed points do not change, and thus the energy (sum of squares of the coordinates defining the vector) of each fixed point is computed and stored. The energy of each variable input point may also be computed. The distance between each pair of fixed and input points is computed based on the respective energies and the dot product.

摘要翻译： 本发明的一个方面利用固定点的坐标不变的事实，因此计算并存储每个固定点的能量（定义矢量的坐标的平方和）。 也可以计算每个可变输入点的能量。 基于相应的能量和点积来计算每对固定点和输入点之间的距离。

公开(公告)号：US06658445B1

公开(公告)日：2003-12-02

申请号：US09614116

申请日：2000-07-11

申请人： Yow-Ling Gau ,  Bor-Chin Wang ,  Ching-Chun Meng

发明人： Yow-Ling Gau ,  Bor-Chin Wang ,  Ching-Chun Meng

IPC分类号： G06F738

CPC分类号： G06F7/552 ,  G06F2207/5525

摘要： An apparatus and method for demodulating a square root of the sum of squares of two inputs I and Q in a digital signal processing are provided. The square root {square root over (I2+Q2)} is approximated by an equation aX +bY, wherein coefficients a and b are special binary numbers. Due to the numbers, the square root {square root over (I2+Q2)} can be quickly computed by the operation of shifting and addition. A plurality of possible approximation values for the coefficients a and b are provided, as well as the use of a comparator to select the maximal one among the possible approximation values.

摘要翻译： 提供了一种用于在数字信号处理中解调两个输入I和Q的平方和的平方根的装置和方法。 平方根（平方根超过（I 2 + Q 2）}）近似为等式aX + bY，其中系数a和b是特殊的二进制数。 由于数字，可以通过移位和相加的操作快速计算平方根（平方根超过（I 2> + 2）}}。 提供了系数a和b的多个可能的近似值，以及使用比较器来选择可能的近似值中的最大值。