公开(公告)号：US6026122A

公开(公告)日：2000-02-15

申请号：US925495

申请日：1997-09-09

申请人： Takashi Kaku ,  Kyoko Hirao ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Kyoko Hirao ,  Hideo Miyazawa

IPC分类号： H03H15/00 ,  H03H17/00 ,  H03H21/00 ,  H03M13/23 ,  H04B3/04 ,  H04L25/03 ,  H04L27/34 ,  H04L5/12 ,  H04L23/02

CPC分类号： H04L27/3411 ,  H04L25/03343 ,  H04L25/4975 ,  H04L27/34

摘要： A transfer process in which, an original vector signal is precoded to an intermediately-precoded vector signal, and the extended modulo operation is performed when the intermediately-precoded vector signal is located outside a predetermined extended-modulo limit area, and the precoded vector signal is transferred through a system having a predetermined filtering characteristic. From the transferred vector signal, the original vector signal is detected, based on a relationship between the vector components of the original vector signal and the transferred vector signal.

摘要翻译： 原始矢量信号被预编码为中间预编码矢量信号的传送处理，当中间预编码矢量信号位于预定的扩展模数限制区域之外时执行扩展模运算，并且预编码矢量信号 通过具有预定滤波特性的系统传送。 根据传送的矢量信号，基于原始矢量信号的矢量分量与传送的矢量信号之间的关系来检测原始矢量信号。

公开(公告)号：US6002712A

公开(公告)日：1999-12-14

申请号：US898493

申请日：1997-07-22

申请人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa

IPC分类号： H03H17/02 ,  H03H17/08 ,  H04B3/06 ,  H04L7/02 ,  H04L27/22 ,  H04B1/38 ,  H03K5/159

CPC分类号： H04L7/0029 ,  H04L7/0087 ,  H04L7/007

摘要： The present invention discloses a timing phase control apparatus which is particularly suitable for use in a modem used for very high speed data transmission employing a metallic line. The timing phase control apparatus includes a timing phase extracting portion to extract timing phase information from an input signal, a timing phase control filter portion to make a timing phase control to the input signal depending upon the timing phase information from the timing phase extracting portion through filter processing using a coefficient operation having a preset impulse response characteristic, and a filter processing coefficient determining portion to determine a coefficient used for the filter processing in the timing phase control filter portion depending upon the timing phase information and information about an approximate expression of the impulse response characteristic. An accuracy of a tap coefficient can be improved while reducing an amount of information about the tap coefficient, which should be stored.

摘要翻译： 本发明公开了一种定时相位控制装置，其特别适用于采用金属线路进行超高速数据传输的调制解调器。 定时相位控制装置包括定时相位提取部分，用于从输入信号提取定时相位信息;定时相位控制滤波器部分，用于根据来自定时相位提取部分的定时相位信息对输入信号进行定时相位控制， 使用具有预设脉冲响应特性的系数操作的滤波处理和滤波处理系数确定部分，以根据定时相位信息确定用于定时相位控制滤波器部分中的滤波处理的系数，以及关于近似表达式的信息 脉冲响应特性。 可以减少抽头系数的精度，同时减少应该存储的抽头系数的信息量。

公开(公告)号：US5719907A

公开(公告)日：1998-02-17

申请号：US534161

申请日：1995-09-26

申请人： Takashi Kaku ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Hideo Miyazawa

IPC分类号： H04B3/04 ,  H04B3/06 ,  H04L1/20 ,  H04L25/02 ,  H04L25/08 ,  H04L27/22 ,  H04L27/38 ,  H04L25/38 ,  H04L5/16

CPC分类号： H04L27/3872 ,  H04L1/205

摘要： The invention provides a phase jitter extraction circuit and a phase jitter cancellation circuit for use with a reception section of a communication apparatus such as a modem used to transmit data using a telephone line or a private line, which are improved in that noise of a signal is prevented from increasing to suppress phase jitters with a high degree of accuracy and high noise components can be suppressed irrespective of the power of the input signal. The phase jitter extraction circuit includes a phase jitter detection section for detecting phase jitters from input/output information of a signal discriminator, a phase jitter forecasting section for forecasting phase jitters which will be produced later from the phase jitters detected by the phase jitter detection section, a selector for selectively outputting the phase jitters detected by the phase jitter detection section or the forecast phase jitters obtained by the phase jitter forecasting section, and a selector control section for discriminating a region of signal points received by the communication apparatus by way of a transmission line and controlling the selector in accordance with a result of the discrimination.

摘要翻译： 本发明提供一种相位抖动提取电路和相位抖动消除电路，用于与诸如调制解调器之类的通信装置的接收部分一起使用，该调制解调器用于使用电话线路或专用线路传输数据， 防止增加以高精度抑制相位抖动，并且与输入信号的功率无关，可以抑制高噪声分量。 相位抖动提取电路包括：相位抖动检测部分，用于从信号鉴别器的输入/输出信息中检测相位抖动;相位抖动预测部分，用于预测稍后将由相位抖动检测部分检测的相位抖动产生的相位抖动; 选择器，用于选择性地输出由相位抖动检测部分检测的相位抖动或由相位抖动预测部分获得的预测相位抖动，以及选择器控制部分，用于通过通信装置接收的信号点的区域 传输线，并根据鉴别结果控制选择器。

公开(公告)号：US5559799A

公开(公告)日：1996-09-24

申请号：US108536

申请日：1993-08-19

申请人： Hiroyasu Murata ,  Hideo Miyazawa ,  Takashi Kaku

发明人： Hiroyasu Murata ,  Hideo Miyazawa ,  Takashi Kaku

IPC分类号： H04L27/00 ,  H04L5/06 ,  H04L27/22 ,  H04L27/233 ,  H04L27/38 ,  H04B1/38 ,  H04J1/14

CPC分类号： H04L5/06 ,  H04L27/2338

摘要： A modulator and demodulator apparatus for use with a network is provided. The modulator and demodulator apparatus comprises a modulation section which includes a timing phase discrimination section for receiving, as an input signal thereto, a demodulation vector signal sampled into a digital value and discriminating to which one of a plurality of regions of a discrimination plane the phase of the input signal belongs. The timing phase discrimination section supplies, as an input to a next processing stage, a rotation vector obtained by rotating an input vector, moves the rotation vector to a quadrant which includes a reference discrimination region of the discrimination plane and performs, when the vector after the movement is not in the reference discrimination region, a predetermined calculation. When the vector after the movement comes to the reference discrimination region, another calculation is performed. This discriminates a timing phase of the input vector from the result of the calculation.

摘要翻译： 提供一种用于网络的调制器和解调器装置。 调制器和解调器装置包括调制部分，其包括定时相位鉴别部分，用于将采样成数字值的解调矢量信号作为输入信号，并将鉴别面的多个区域中的哪一个区分为相位 的输入信号属于。 定时相位识别部将作为输入向下一个处理级的输入提供通过旋转输入矢量而获得的旋转矢量，将旋转矢量移动到包括鉴别面的参考识别区域的象限，并且当后向量 运动不在参考识别区域中，所以是预定的计算。 当运动之后的矢量进入参考识别区域时，进行另一次计算。 这样就从计算结果中辨别出输入向量的定时相位。

公开(公告)号：US06898256B2

公开(公告)日：2005-05-24

申请号：US10319927

申请日：2002-12-12

申请人： Takashi Kaku ,  Takahiro Kurakata ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Takahiro Kurakata ,  Hideo Miyazawa

IPC分类号： H04L7/02 ,  H04L7/06 ,  H04L27/26 ,  H04L27/34 ,  H04L7/00

CPC分类号： H04L27/2613 ,  H04J7/00 ,  H04L7/06 ,  H04L27/2656 ,  H04L27/3455

摘要： In a synchronization method and apparatus in a data transmission using a transparent transmission line, a periodic amplitude modulation is applied, or a zero-point is inserted, as a synchronizing signal to a transmission signal point on a transmission side at a preceding stage of a transparent transmission line. Also, in case of a frame synchronization, a power value of a received signal is calculated on a reception side of the above-mentioned transparent transmission line and the synchronizing signal is vectorized using the power values whose phases are different from each other by 90 degrees on a time axis.

摘要翻译： 在使用透明传输线的数据传输的同步方法和装置中，施加周期性幅度调制或插入零点作为同步信号到发送侧的发送信号点，在前一阶段 透明传输线。 此外，在帧同步的情况下，在上述透明传输线的接收侧计算接收信号的功率值，并且使用相位彼此不同的功率值向量化同步信号90度 在时间轴上。

公开(公告)号：US06882684B2

公开(公告)日：2005-04-19

申请号：US09756793

申请日：2001-01-10

申请人： Takashi Kaku ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Hideo Miyazawa

IPC分类号： H04L27/38 ,  H03G3/30 ,  H04L27/08 ,  H04L27/34 ,  H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L27/34 ,  H03G3/3089 ,  H04L27/08

摘要： An automatic gain control circuit includes a first portion which calculates a first error amount, and a second portion which calculates a second error amount. Both calculated error amount is sent to a determination module. Further, an integrator integrates an error amount, a difference between a power of an input signal and an average power of an eye pattern for example. The determination determines whether the integrated error amount exceeds a predetermined value or not, and output either of the first error amount and the second error amount based on the determination.

摘要翻译： 自动增益控制电路包括计算第一误差量的第一部分和计算第二误差量的第二部分。 两个计算出的错误量被发送到确定模块。 此外，积分器将误差量，输入信号的功率与眼图的平均功率之间的差异进行积分。 该判定是否确定积分误差量是否超过预定值，并且基于该确定来输出第一误差量和第二误差量中的任一个。

公开(公告)号：US06377647B1

公开(公告)日：2002-04-23

申请号：US09205804

申请日：1998-12-04

申请人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa

IPC分类号： H03D324

CPC分类号： H03L7/091 ,  H04L7/0331

摘要： A PLL circuit that causes an internal oscillation signal to lock to an external input clock signal, and is capable of suppressing jitter. The PLL circuit includes a frequency dividing circuit for frequency-dividing an input clock signal; a voltage-controlled oscillator; a missing-pulse clock signal creation circuit for creating, based on an output signal of the voltage-controlled oscillator, a missing-pulse clock signal having a higher speed than that of an output signal of the frequency dividing circuit and having a periodic missing-pulse portion; a phase comparator circuit for sampling the output signal of the frequency dividing circuit by using the missing-pulse clock signal; a shift register for storing a change in the output signal of the phase comparator circuit; and a digital signal processing circuit for converting a value stored in the shift register into a phase difference, and for controlling the input voltage to the voltage-controlled oscillator based on the phase difference.

摘要翻译： PLL电路使内部振荡信号锁定到外部输入时钟信号，并且能够抑制抖动。 PLL电路包括用于对输入时钟信号进行分频的分频电路; 压控振荡器; 一个缺失脉冲时钟信号产生电路，用于根据压控振荡器的输出信号创建一个具有比分频电路的输出信号高的缺失脉冲时钟信号， 脉冲部分 相位比较器电路，用于通过使用缺失脉冲时钟信号对分频电路的输出信号进行采样; 移位寄存器，用于存储相位比较器电路的输出信号的变化; 以及数字信号处理电路，用于将存储在移位寄存器中的值转换为相位差，并且用于基于相位差控制到压控振荡器的输入电压。

公开(公告)号：US6104758A

公开(公告)日：2000-08-15

申请号：US925181

申请日：1997-09-09

申请人： Takashi Kaku ,  Kyoko Hirao ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Kyoko Hirao ,  Hideo Miyazawa

IPC分类号： H03H15/00 ,  H03H17/00 ,  H03H21/00 ,  H03M13/23 ,  H04B3/04 ,  H04L25/03 ,  H04L27/34 ,  H04L5/12

CPC分类号： H04L27/3411 ,  H04L25/03343 ,  H04L25/4975 ,  H04L27/34

摘要： A transfer process in which, an original vector signal is precoded to an intermediately-precoded vector signal, and the extended modulo operation is performed when the intermediately-precoded vector signal is located outside a predetermined extended-modulo limit area, and the precoded vector signal is transferred through a system having a predetermined filtering characteristic. From the transferred vector signal, the original vector signal is detected, based on a relationship between the vector components of the original vector signal and the transferred vector signal.

公开(公告)号：US5963593A

公开(公告)日：1999-10-05

申请号：US825067

申请日：1997-03-27

申请人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa ,  Yuri Nigaki

发明人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa ,  Yuri Nigaki

IPC分类号： H03H17/00 ,  H04B3/04 ,  H04B3/10 ,  H03H7/40 ,  H03H5/00

CPC分类号： H04B3/04 ,  H04L25/03885

摘要： A method of controlling a line equalizer such as a modem includes an extracting step of extracting plural tone signals each superimposed on a transmission signal and having a specific frequency component; a judging step of judging levels of the extracted tone signals; and a controlling step of controlling characteristic of a line equalizer which equalizes a receive signal, based on the levels of the judged tone signals. A line equalizer is controlled without performing an exchange of a training signal prior to starting a data transmission and without increasing the amount of hardware of a modem or the like.

摘要翻译： 一种控制诸如调制解调器之类的线路均衡器的方法包括一个提取步骤，提取叠加在传输信号上并具有特定频率分量的多个音调信号; 判断步骤，用于判断所提取的音调信号的电平; 以及控制步骤，基于所判断的音调信号的电平来控制均衡接收信号的线均衡器的特性。 在开始数据传输之前不必执行训练信号的交换，而不增加调制解调器等的硬件量，可以控制线路均衡器。

公开(公告)号：US5757865A

公开(公告)日：1998-05-26

申请号：US553990

申请日：1995-11-06

申请人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Noboru Kawada ,  Hideo Miyazawa

IPC分类号： H04L27/38 ,  H04L27/00 ,  H04L27/22 ,  H04L27/233 ,  H04L27/06

CPC分类号： H04L27/2332 ,  H04L2027/003 ,  H04L2027/0055

摘要： The invention provides a carrier phase control circuit which can eliminate a phase intercept fluctuation so that, when the carrier phase control circuit is applied to a very high speed modem having a communication speed of, for example, 28.8 kbps, occurrence of a communication error can be suppressed and the modem has an improved characteristic. The carrier phase control circuit is provided on a reception side of a communication apparatus and interposed between an automatic equalizer and a signal decision section. The carrier phase control circuit includes a frequency offset removal section for predicting and removing an offset of a frequency of a transmission signal based on an output of the automatic equalizer, and a phase intercept variation removal section for predicting and removing a phase intercept variation of the transmission signal based on an output of the frequency offset removal section and inputting a resulted signal as an output thereof to the signal decision section.

摘要翻译： 本发明提供了一种载波相位控制电路，其可以消除相位截距波动，使得当载波相位控制电路被应用于具有例如28.8kbps的通信速度的非常高速的调制解调器时，可能发生通信错误 被抑制，调制解调器具有改进的特性。 载波相位控制电路设置在通信装置的接收侧，并插入在自动均衡器和信号判定部分之间。 载波相位控制电路包括：频率偏移消除部分，用于基于自动均衡器的输出来预测和去除发送信号频率的偏移;相位截距变化去除部分，用于预测和去除发送信号的相位截距变化， 基于频率偏移去除部的输出的发送信号，并将得到的信号作为其输出输入到信号判定部。