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    High-K (HK)/metal gate (MG) (HK/MG) multi-time programmable (MTP) switching devices, and related systems and methods
    1.
    发明授权
    High-K (HK)/metal gate (MG) (HK/MG) multi-time programmable (MTP) switching devices, and related systems and methods 有权
    高K（HK）/金属门（MG）（HK / MG）多时间可编程（MTP）开关器件及相关系统和方法

    公开(公告)号：US09413349B1

    公开(公告)日：2016-08-09

    申请号：US14676228

    申请日：2015-04-01

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Xiao Lu ,  Xiaonan Chen ,  Zhongze Wang ,  Choh Fei Yeap

    IPC: G11C16/10 ,  H03K17/687 ,  H01L29/792 ,  H01L29/51 ,  H01L27/115 ,  G11C16/04

    CPC classification number: H03K17/687 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/1052 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/792

    Abstract: Aspects disclosed in the detailed description include high-k (HK)/metal gate (MG) (HK/MG) multi-time programmable (MTP) switching devices, and related systems and methods. One type of HK/MG MTP switching device is an MTP metal-oxide semiconductor (MOS) field-effect transistor (MOSFET). When the MTP MOSFET is programmed, a charge trap may build up in the MTP MOSFET due to a switching electrical current induced by a switching voltage. The charge trap reduces the switching window and endurance of the MTP MOSFET, thus reducing reliability in accessing the information stored in the MTP MOSFET. In this regard, an HK/MG MTP switching device comprising the MTP MOSFET is configured to eliminate the switching electrical current when the MTP MOSFET is programmed. By eliminating the switching electrical current, it is possible to avoid a charge trap in the MTP MOSFET, thus restoring the switching window and endurance of the MTP MOSFET for reliable information access.

    Abstract translation: 在详细描述中公开的方面包括高k（HK）/金属门（MG）（HK / MG）多时间可编程（MTP）交换设备以及相关的系统和方法。 一种类型的HK / MG MTP开关器件是MTP金属氧化物半导体（MOS）场效应晶体管（MOSFET）。 当编程MTP MOSFET时，由于开关电压引起的开关电流，电荷陷阱可能会积累在MTP MOSFET中。 电荷阱减少了MTP MOSFET的开关窗口和耐久性，从而降低了访问存储在MTP MOSFET中的信息的可靠性。 在这方面，包括MTP MOSFET的HK / MG MTP开关器件被配置为在编程MTP MOSFET时消除开关电流。 通过消除开关电流，可以避免MTP MOSFET中的电荷陷阱，从而恢复MTP MOSFET的开关窗口和耐用性，从而实现可靠的信息访问。

    MAGNETIC AUTOMATIC TESTING EQUIPMENT (ATE) MEMORY TESTER
    3.
    发明申请
    MAGNETIC AUTOMATIC TESTING EQUIPMENT (ATE) MEMORY TESTER 审中-公开
    磁性自动测试设备（ATE）存储器测试仪

    公开(公告)号：US20140139209A1

    公开(公告)日：2014-05-22

    申请号：US13680432

    申请日：2012-11-19

    Applicant: QUALCOMM INCORPORATED

    Inventor： Kangho Lee ,  Xiao Lu ,  Wah Nam Hsu ,  Seung H. Kang

    IPC: G01R33/02

    CPC classification number: G01R33/02 ,  G11C11/16 ,  G11C29/56016

    Abstract: Several novel features pertain to an automatic testing equipment (ATE) memory tester that includes a load board, a projected-field electromagnet, a positioning mechanism and a memory tester. The load board is for coupling to a die package that includes a magnetoresistive random access memory (MRAM) having several cells, where each cell includes a magnetic tunnel junction (MTJ). The projected-field electromagnet is for applying a portion of a magnetic field across the MRAM. The portion of the magnetic field may be substantially uniform. The positioning mechanism is coupled to the electromagnet and the load board, and is configured to position the electromagnet vertically about (above/below) the die package when the die package is coupled to the load board. The memory tester is coupled to the load board. The memory tester is for testing the MRAM when the substantially uniform portion of the magnetic field is applied across the MRAM.

    Abstract translation: 一些新颖的功能涉及自动测试设备（ATE）存储器测试器，其包括负载板，投射场电磁体，定位机构和存储器测试器。 负载板用于耦合到包括具有几个电池的磁阻随机存取存储器（MRAM）的管芯封装，其中每个电池包括磁性隧道结（MTJ）。 投射场电磁铁用于在MRAM上施加磁场的一部分。 磁场的部分可以是基本均匀的。 定位机构联接到电磁体和负载板，并且被配置为当模具封装耦合到负载板时，将电磁铁垂直地围绕模具封装（上/下）定位。 存储器测试器耦合到负载板。 当磁场的基本上均匀的部分被施加在MRAM上时，存储器测试器用于测试MRAM。

    DATA RETENTION ERROR DETECTION SYSTEM
    6.
    发明申请
    DATA RETENTION ERROR DETECTION SYSTEM 有权
    数据保持错误检测系统

    公开(公告)号：US20150179281A1

    公开(公告)日：2015-06-25

    申请号：US14138059

    申请日：2013-12-21

    Applicant: QUALCOMM Incorporated

    Inventor： Xiao Lu ,  Wah Nam Hsu

    IPC: G11C29/10 ,  G06F11/07

    CPC classification number: G11C29/10 ,  G06F11/073 ,  G11C11/16 ,  G11C29/50016

    Abstract: A particular method includes selecting a threshold data retention time of a magnetic tunnel junction (MTJ) memory cell. A pinned layer of the MTJ memory cell has a first direction of magnetization, and a free layer of the MTJ memory cell has a second direction of magnetization. An external magnetic field that has a third direction of magnetization that is opposite to the second direction of magnetization is applied to the MTJ memory cell. A strength of the external magnetic field is determined based on the threshold data retention time. Subsequent to applying the external magnetic field, a read operation is performed on the MTJ memory cell to determine a logic value of the MTJ memory cell. The method further includes determining whether the MTJ memory cell is subject to a data retention error corresponding to the threshold data retention time based on the logic value.

    Abstract translation: 一种特定方法包括选择磁性隧道结（MTJ）存储单元的阈值数据保留时间。 MTJ存储单元的钉扎层具有第一磁化方向，并且MTJ存储单元的自由层具有第二磁化方向。 具有与第二磁化方向相反的第三磁化方向的外部磁场施加到MTJ存储单元。 基于阈值数据保持时间确定外部磁场的强度。 在施加外部磁场之后，对MTJ存储单元执行读取操作以确定MTJ存储器单元的逻辑值。 该方法还包括基于逻辑值确定MTJ存储器单元是否受到与阈值数据保留时间相对应的数据保留错误。

    Data retention error detection system
    7.
    发明授权
    Data retention error detection system 有权
    数据保留错误检测系统

    公开(公告)号：US09159455B2

    公开(公告)日：2015-10-13

    申请号：US14138059

    申请日：2013-12-21

    Applicant: QUALCOMM Incorporated

    Inventor： Xiao Lu ,  Wah Nam Hsu

    IPC: G11C11/00 ,  G11C29/10 ,  G06F11/07 ,  G11C29/50 ,  G11C11/16

    CPC classification number: G11C29/10 ,  G06F11/073 ,  G11C11/16 ,  G11C29/50016

    Abstract: A particular method includes selecting a threshold data retention time of a magnetic tunnel junction (MTJ) memory cell. A pinned layer of the MTJ memory cell has a first direction of magnetization, and a free layer of the MTJ memory cell has a second direction of magnetization. An external magnetic field that has a third direction of magnetization that is opposite to the second direction of magnetization is applied to the MTJ memory cell. A strength of the external magnetic field is determined based on the threshold data retention time. Subsequent to applying the external magnetic field, a read operation is performed on the MTJ memory cell to determine a logic value of the MTJ memory cell. The method further includes determining whether the MTJ memory cell is subject to a data retention error corresponding to the threshold data retention time based on the logic value.

    Abstract translation: 一种特定方法包括选择磁性隧道结（MTJ）存储单元的阈值数据保留时间。 MTJ存储单元的钉扎层具有第一磁化方向，并且MTJ存储单元的自由层具有第二磁化方向。 具有与第二磁化方向相反的第三磁化方向的外部磁场施加到MTJ存储单元。 基于阈值数据保持时间确定外部磁场的强度。 在施加外部磁场之后，对MTJ存储单元执行读取操作以确定MTJ存储器单元的逻辑值。 该方法还包括基于逻辑值确定MTJ存储器单元是否受到与阈值数据保留时间相对应的数据保留错误。

    Logic high-dielectric-constant (HK) metal-gate (MG) one-time-programming (OTP) memory device sensing method
    9.
    发明授权
    Logic high-dielectric-constant (HK) metal-gate (MG) one-time-programming (OTP) memory device sensing method 有权
    逻辑高介电常数（HK）金属栅极（MG）一次编程（OTP）存储器件感测方法

    公开(公告)号：US09245648B1

    公开(公告)日：2016-01-26

    申请号：US14498519

    申请日：2014-09-26

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Xiaonan Chen ,  Xiao Lu

    IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16

    CPC classification number: G11C17/18 ,  G11C11/5692 ,  G11C17/16

    Abstract: In a one-time-programming (OTP) memory cell, dual-voltage sensing is utilized to determine whether the memory cell has experienced a non/soft breakdown or a hard breakdown. The drain current of the memory cell is read when the gate voltage is at a first predetermined voltage, and if the read drain current is greater than a predetermined current level, then a hard breakdown is detected. One or more additional readings of the current may be obtained to determine that a hard breakdown has occurred. If the read drain current is less than the predetermined current level, then a non/soft breakdown is detected. The threshold voltage of the memory cell may be shifted, and a second reading of the drain current may be obtained when the gate voltage is at a second predetermined voltage in case the memory cell experiences a non/soft breakdown.

    Abstract translation: 在一次编程（OTP）存储器单元中，利用双电压感测来确定存储器单元是否经历了非/软故障或硬故障。 当栅极电压处于第一预定电压时，读取存储单元的漏极电流，并且如果读取的漏极电流大于预定电流电平，则检测到硬故障。 可以获得电流的一个或多个附加读数以确定发生了硬故障。 如果读漏极电流小于预定电流电平，则检测到非/软击穿。 当存储器单元经历非/软击穿时，当栅极电压处于第二预定电压时，可以移位存储单元的阈值电压，并且可以获得漏极电流的第二读数。

    MAGNETIC AUTOMATIC TEST EQUIPMENT (ATE) MEMORY TESTER DEVICE AND METHOD EMPLOYING TEMPERATURE CONTROL
    10.
    发明申请
    MAGNETIC AUTOMATIC TEST EQUIPMENT (ATE) MEMORY TESTER DEVICE AND METHOD EMPLOYING TEMPERATURE CONTROL 有权
    磁性自动测试设备（ATE）存储器测试设备和采用温度控制的方法

    公开(公告)号：US20140254251A1

    公开(公告)日：2014-09-11

    申请号：US13787938

    申请日：2013-03-07

    Applicant: QUALCOMM INCORPORATED

    Inventor： Kangho Lee ,  Wah Nam Hsu ,  Xiao Lu ,  Seung H. Kang

    IPC: G11C29/04

    CPC classification number: G11C29/04 ,  G11C7/04 ,  G11C11/16 ,  G11C29/00 ,  G11C29/56016

    Abstract: In a particular embodiment, a method includes controlling a temperature within a chamber while applying a magnetic field. A device including a memory array is located in the chamber. The method includes applying a magnetic field to the memory array and testing the memory array during application of the magnetic field to the memory array at a target temperature.

    Abstract translation: 在特定实施例中，一种方法包括在施加磁场的同时控制室内的温度。 包括存储器阵列的装置位于腔室中。 该方法包括在存储器阵列中施加磁场并在目标温度下将磁场施加到存储器阵列期间测试存储器阵列。

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