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    HIGH ASPECT RATIO ETCH WITH INFINITE SELECTIVITY
    2.
    发明申请
    HIGH ASPECT RATIO ETCH WITH INFINITE SELECTIVITY 有权

    公开(公告)号：US20230081817A1

    公开(公告)日：2023-03-16

    申请号：US17904046

    申请日：2021-01-29

    申请人： Lam Research Corporation

    发明人： Leonid Belau ,  Eric A. Hudson

    IPC分类号： H01J37/32

    摘要： Provided herein are methods and apparatus for processing a substrate by exposing the substrate to plasma to simultaneously (i) etch features in an underlying material (e.g., which includes one or more dielectric materials), and (ii) deposit a upper mask protector layer on a mask positioned over the dielectric material, where the upper mask protector layer forms on top of the mask in a selective vertically-oriented directional deposition. Such methods and apparatus may be used to achieve infinite etch selectivity, even when etching high aspect ratio features.

    Mask shrink layer for high aspect ratio dielectric etch
    3.
    发明授权
    Mask shrink layer for high aspect ratio dielectric etch 有权

    公开(公告)号：US10431458B2

    公开(公告)日：2019-10-01

    申请号：US15359362

    申请日：2016-11-22

    申请人： Lam Research Corporation

    发明人： Eric A. Hudson ,  Mark H. Wilcoxson ,  Kalman Pelhos ,  Hyunjong Shim ,  Merrett Wong

    IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/67 ,  H01J37/32 ,  H01L21/677 ,  H01L21/3205

    摘要： Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. In many embodiments, a mask shrink layer is deposited on a patterned mask layer to thereby narrow the openings in the mask layer. The mask shrink layer may be deposited through a vapor deposition process including, but not limited to, atomic layer deposition or chemical vapor deposition. The mask shrink layer can result in narrower, more vertically uniform etched features. In some embodiments, etching is completed in a single etch step. In some other embodiments, the etching may be done in stages, cycled with a deposition step designed to deposit a protective sidewall coating on the partially etched features. Metal-containing films are particularly suitable as mask shrink films and protective sidewall coatings.

    TECHNIQUE TO DEPOSIT SIDEWALL PASSIVATION FOR HIGH ASPECT RATIO CYLINDER ETCH
    6.
    发明申请
    TECHNIQUE TO DEPOSIT SIDEWALL PASSIVATION FOR HIGH ASPECT RATIO CYLINDER ETCH 有权
    用于高比例气缸蚀刻的沉积技术

    公开(公告)号：US20160268141A1

    公开(公告)日：2016-09-15

    申请号：US15163123

    申请日：2016-05-24

    申请人： Lam Research Corporation

    发明人： Eric A. Hudson

    IPC分类号： H01L21/311 ,  C23C16/455 ,  C23C16/52 ,  H01J37/32 ,  C23C16/50

    CPC分类号： H01L21/31138 ,  C23C16/00 ,  C23C16/045 ,  C23C16/45525 ,  C23C16/45544 ,  C23C16/50 ,  C23C16/52 ,  H01J37/32009 ,  H01J37/32091 ,  H01J37/32449 ,  H01J37/32899 ,  H01J2237/334 ,  H01L21/02118 ,  H01L21/0212 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/1087

    摘要： Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants and/or reaction mechanisms that result in substantially complete sidewall coating at relatively low temperatures without the use of plasma. In some cases the protective coating is deposited using molecular layer deposition techniques. In certain implementations the protective coating is fluorinated.

    摘要翻译： 本文的各种实施例涉及用于在半导体衬底上的电介质材料中形成凹陷特征的方法，装置和系统。 以循环方式采用分离的蚀刻和沉积操作。 每个蚀刻操作部分地蚀刻该特征。 每个沉积操作在特征的侧壁上形成保护涂层，以防止在蚀刻操作期间电介质材料的横向蚀刻。 保护涂层可以使用沿着侧壁的大致整个长度形成保护涂层的方法进行沉积。 可以使用特定的反应物和/或反应机理来沉积保护性涂层，所述反应物和/或反应机理在不使用等离子体的情况下在相对低的温度下导致基本上完全的侧壁涂覆。 在某些情况下，使用分子层沉积技术沉积保护涂层。 在某些实施方式中，保护涂层是氟化的。

    ION TO NEUTRAL CONTROL FOR WAFER PROCESSING WITH DUAL PLASMA SOURCE REACTOR
    8.
    发明申请
    ION TO NEUTRAL CONTROL FOR WAFER PROCESSING WITH DUAL PLASMA SOURCE REACTOR 有权
    使用双等离子体源反应器进行中和控制

    公开(公告)号：US20150083582A1

    公开(公告)日：2015-03-26

    申请号：US14033241

    申请日：2013-09-20

    申请人： Lam Research Corporation

    发明人： Rajinder Dhindsa ,  Sang Ki Nam ,  Alexei Marakhtanov ,  Eric A. Hudson

    IPC分类号： H01L21/67 ,  H01L21/3065

    CPC分类号： H01L21/67069 ,  H01J37/32357 ,  H01J37/32422 ,  H01J2237/334 ,  H01L21/3065

    摘要： The disclosed techniques relate to methods and apparatus for etching a substrate. A plate assembly divides a reaction chamber into a lower and upper sub-chamber. The plate assembly includes an upper and lower plate having apertures therethrough. When the apertures in the upper and lower plates are aligned, ions and neutral species may travel through the plate assembly into the lower sub-chamber. When the apertures are not aligned, ions are prevented from passing through the assembly while neutral species are much less affected. Thus, the ratio of ion flux:neutral flux may be tuned by controlling the amount of area over which the apertures are aligned. In certain embodiments, one plate of the plate assembly is implemented as a series of concentric, independently movable injection control rings. Further, in some embodiments, the upper sub-chamber is implemented as a series of concentric plasma zones separated by walls of insulating material.

    摘要翻译： 所公开的技术涉及用于蚀刻衬底的方法和设备。 板组件将反应室分成下部和上部副室。 板组件包括具有穿过其中的孔的上板和下板。 当上板和下板中的孔对齐时，离子和中性物质可以穿过板组件进入下子室。 当孔不对齐时，防止离子通过组件，而中性物质受影响较小。 因此，可以通过控制孔对准的面积的量来调节离子通量：中性流量的比率。 在某些实施例中，板组件的一个板被实现为一系列同心的，可独立移动的喷射控制环。 此外，在一些实施例中，上部子室被实现为由绝缘材料的壁隔开的一系列同心等离子体区域。

    PASSIVATION CHEMISTRY FOR PLASMA ETCHING
    9.
    发明公开
    PASSIVATION CHEMISTRY FOR PLASMA ETCHING 审中-公开

    公开(公告)号：US20230335378A1

    公开(公告)日：2023-10-19

    申请号：US18003138

    申请日：2021-09-17

    申请人： Lam Research Corporation

    发明人： Eric A. Hudson

    IPC分类号： H01J37/32 ,  H01L21/311 ,  H01L21/3213

    CPC分类号： H01J37/32449 ,  H01L21/31116 ,  H01L21/32136 ,  H01J2237/2001 ,  H01J2237/334

    摘要： Various embodiments herein relate to methods and apparatus for etching a recessed feature in a material on a substrate. For example, the methods may include (a) flowing a gas mixture into a processing chamber, where the gas mixture includes an etch component and a passivation component, and where the passivation component includes particular elements and/or species and/or is provided under particular conditions; (b) generating a plasma from the gas mixture in the processing chamber; and (c) exposing the substrate to the plasma and etching the recessed feature in the material on the substrate. In many cases, the material being etched on the substrate includes dielectric material and/or an electrically conductive material.