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1.发明申请公开(公告)号：US20170170026A1
公开(公告)日：2017-06-15
申请号：US15440842
申请日：2017-02-23
IPC分类号： H01L21/3065 , H01L21/768 , H01L21/285 , H01L27/11556 , H01L27/11582 , H01L27/108 , H01L21/67 , C23C16/02 , C23C16/04 , C23C16/38 , C23C16/40 , C23C16/455 , C23C16/505 , C23C16/44 , C23C16/56 , H01L21/311
CPC分类号： H01L21/30655 , C23C16/0209 , C23C16/0245 , C23C16/045 , C23C16/38 , C23C16/40 , C23C16/4408 , C23C16/45542 , C23C16/45546 , C23C16/505 , C23C16/56 , H01J37/32165 , H01J37/32568 , H01J37/32577 , H01J37/32715 , H01J37/32908 , H01L21/02175 , H01L21/02274 , H01L21/0228 , H01L21/28556 , H01L21/31116 , H01L21/67069 , H01L21/68785 , H01L21/76802 , H01L21/76843 , H01L27/10847 , H01L27/11556 , H01L27/11582
摘要： Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation. In some cases, a bilayer approach may be used to deposit the protective coating on sidewalls of partially etched features.
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公开(公告)号：US20170076945A1
公开(公告)日：2017-03-16
申请号：US15359362
申请日：2016-11-22
IPC分类号： H01L21/033 , H01L21/67 , H01J37/32 , H01L21/311
CPC分类号： H01L21/0338 , H01J37/32091 , H01J37/32366 , H01J37/3244 , H01J37/32568 , H01J37/32715 , H01J37/32733 , H01J37/32908 , H01J2237/334 , H01L21/0332 , H01L21/0335 , H01L21/0337 , H01L21/31116 , H01L21/31144 , H01L21/3205 , H01L21/67069 , H01L21/6719 , H01L21/67201 , H01L21/67207 , H01L21/67745
摘要： Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. In many embodiments, a mask shrink layer is deposited on a patterned mask layer to thereby narrow the openings in the mask layer. The mask shrink layer may be deposited through a vapor deposition process including, but not limited to, atomic layer deposition or chemical vapor deposition. The mask shrink layer can result in narrower, more vertically uniform etched features. In some embodiments, etching is completed in a single etch step. In some other embodiments, the etching may be done in stages, cycled with a deposition step designed to deposit a protective sidewall coating on the partially etched features. Metal-containing films are particularly suitable as mask shrink films and protective sidewall coatings.
摘要翻译： 本文的各种实施例涉及用于在半导体衬底上的电介质堆叠中形成凹陷特征的方法，装置和系统。 在许多实施例中，掩模收缩层沉积在图案化掩模层上，从而使掩模层中的开口变窄。 掩模收缩层可通过包括但不限于原子层沉积或化学气相沉积的气相沉积工艺沉积。 掩模收缩层可以导致较窄的，更垂直均匀的蚀刻特征。 在一些实施例中，在单个蚀刻步骤中完成蚀刻。 在一些其它实施例中，蚀刻可以分阶段进行，循环使用沉积步骤设计成在部分蚀刻的特征上沉积保护性侧壁涂层。 含金属膜特别适合作为掩模收缩膜和保护性侧壁涂层。
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公开(公告)号：US09543148B1
公开(公告)日：2017-01-10
申请号：US14842733
申请日：2015-09-01
IPC分类号： H01L21/311 , H01L21/3065 , H01L21/033 , H01L21/67 , H01J37/32
CPC分类号： H01L21/0338 , H01J37/32091 , H01J37/32366 , H01J37/3244 , H01J37/32568 , H01J37/32715 , H01J37/32733 , H01J37/32908 , H01J2237/334 , H01L21/0332 , H01L21/0335 , H01L21/0337 , H01L21/31116 , H01L21/31144 , H01L21/3205 , H01L21/67069 , H01L21/6719 , H01L21/67201 , H01L21/67207 , H01L21/67745
摘要： Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. In many embodiments, a mask shrink layer is deposited on a patterned mask layer to thereby narrow the openings in the mask layer. The mask shrink layer may be deposited through a vapor deposition process including, but not limited to, atomic layer deposition or chemical vapor deposition. The mask shrink layer can result in narrower, more vertically uniform etched features. In some embodiments, etching is completed in a single etch step. In some other embodiments, the etching may be done in stages, cycled with a deposition step designed to deposit a protective sidewall coating on the partially etched features. Metal-containing films are particularly suitable as mask shrink films and protective sidewall coatings.
摘要翻译： 本文的各种实施例涉及用于在半导体衬底上的电介质堆叠中形成凹陷特征的方法，装置和系统。 在许多实施例中，掩模收缩层沉积在图案化掩模层上，从而使掩模层中的开口变窄。 掩模收缩层可通过包括但不限于原子层沉积或化学气相沉积的气相沉积工艺沉积。 掩模收缩层可以导致较窄的，更垂直均匀的蚀刻特征。 在一些实施例中，在单个蚀刻步骤中完成蚀刻。 在一些其它实施例中，蚀刻可以分阶段进行，循环使用沉积步骤设计成在部分蚀刻的特征上沉积保护性侧壁涂层。 含金属膜特别适合作为掩模收缩膜和保护性侧壁涂层。
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4.发明申请TECHNIQUE TO DEPOSIT METAL-CONTAINING SIDEWALL PASSIVATION FOR HIGH ASPECT RATIO CYLINDER ETCH 有权用于高比例圆柱体蚀刻的金属含金属钝化技术公开(公告)号：US20160163558A1
公开(公告)日：2016-06-09
申请号：US14803578
申请日：2015-07-20
IPC分类号： H01L21/3065 , H01L21/67 , H01L21/02
CPC分类号： H01L21/30655 , C23C16/0209 , C23C16/0245 , C23C16/045 , C23C16/38 , C23C16/40 , C23C16/4408 , C23C16/45542 , C23C16/45546 , C23C16/505 , C23C16/56 , H01J37/32165 , H01J37/32568 , H01J37/32577 , H01J37/32715 , H01J37/32908 , H01L21/02175 , H01L21/02274 , H01L21/0228 , H01L21/28556 , H01L21/31116 , H01L21/67069 , H01L21/68785 , H01L21/76802 , H01L21/76843 , H01L27/10847 , H01L27/11556 , H01L27/11582
摘要： Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation. In some cases, a bilayer approach may be used to deposit the protective coating on sidewalls of partially etched features.
摘要翻译： 本文的各种实施例涉及用于在半导体衬底上的电介质堆叠中形成凹陷特征的方法，装置和系统。 以循环方式采用分离的蚀刻和沉积操作。 每个蚀刻操作部分地蚀刻该特征。 每个沉积操作在特征的侧壁上形成保护涂层（例如，含金属的涂层），以防止在蚀刻操作期间电介质材料的横向蚀刻。 保护涂层可以使用沿着侧壁的大致整个长度形成保护涂层的方法进行沉积。 可以使用导致基本上完全的侧壁涂层的特定反应机理来沉积保护性涂层。 已经显示含金属涂层在蚀刻操作期间提供特别好的抗横向蚀刻性能。 在一些情况下，可以使用双层方法将保护涂层沉积在部分蚀刻特征的侧壁上。
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5.发明授权公开(公告)号：US10170323B2
公开(公告)日：2019-01-01
申请号：US15440842
申请日：2017-02-23
IPC分类号： H01L21/3065 , H01L21/02 , H01L21/67 , H01L21/687 , H01J37/32 , H01L21/311 , C23C16/02 , C23C16/04 , C23C16/38 , C23C16/40 , C23C16/44 , C23C16/455 , C23C16/505 , C23C16/56 , H01L21/285 , H01L21/768 , H01L27/108 , H01L27/11556 , H01L27/11582
摘要： Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation. In some cases, a bilayer approach may be used to deposit the protective coating on sidewalls of partially etched features.
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公开(公告)号：US10431458B2
公开(公告)日：2019-10-01
申请号：US15359362
申请日：2016-11-22
IPC分类号： H01L21/033 , H01L21/311 , H01L21/67 , H01J37/32 , H01L21/677 , H01L21/3205
摘要： Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. In many embodiments, a mask shrink layer is deposited on a patterned mask layer to thereby narrow the openings in the mask layer. The mask shrink layer may be deposited through a vapor deposition process including, but not limited to, atomic layer deposition or chemical vapor deposition. The mask shrink layer can result in narrower, more vertically uniform etched features. In some embodiments, etching is completed in a single etch step. In some other embodiments, the etching may be done in stages, cycled with a deposition step designed to deposit a protective sidewall coating on the partially etched features. Metal-containing films are particularly suitable as mask shrink films and protective sidewall coatings.
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7.发明授权公开(公告)号：US09620377B2
公开(公告)日：2017-04-11
申请号：US14803578
申请日：2015-07-20
IPC分类号： H01L21/3065 , H01L21/02 , H01L21/67 , H01L21/687
CPC分类号： H01L21/30655 , C23C16/0209 , C23C16/0245 , C23C16/045 , C23C16/38 , C23C16/40 , C23C16/4408 , C23C16/45542 , C23C16/45546 , C23C16/505 , C23C16/56 , H01J37/32165 , H01J37/32568 , H01J37/32577 , H01J37/32715 , H01J37/32908 , H01L21/02175 , H01L21/02274 , H01L21/0228 , H01L21/28556 , H01L21/31116 , H01L21/67069 , H01L21/68785 , H01L21/76802 , H01L21/76843 , H01L27/10847 , H01L27/11556 , H01L27/11582
摘要： Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation. In some cases, a bilayer approach may be used to deposit the protective coating on sidewalls of partially etched features.
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