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    Apparatus and method for analog-to-digital conversion
    2.
    发明授权
    Apparatus and method for analog-to-digital conversion 有权

    公开(公告)号：US11038516B1

    公开(公告)日：2021-06-15

    申请号：US16886817

    申请日：2020-05-29

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Ramon Sanchez ,  Albert Molina ,  Martin Clara ,  Daniel Gruber ,  Matteo Camponeschi

    IPC: H03M1/10 ,  H03M1/34 ,  H03M1/06

    Abstract: An apparatus and method for analog-to-digital conversion. The apparatus includes a first analog-to-digital converter (ADC), a second ADC, and a calibration unit. The first ADC is configured to sample an input analog signal at a first sampling frequency. The second ADC is configured to sample the input analog signal at a second sampling frequency. The second sampling frequency is a fraction of the first sampling frequency. The calibration unit is configured to correct a distortion incurred in an output of the first ADC based on an output of the second ADC. The first ADC may be a time-interleaved ADC. The second ADC may be an extra sub-ADC of the time-interleaved ADC. The second ADC may be configured to sample the input analog signal at random sampling phases. A dithering noise may be added to the input analog signal of the second ADC. The calibration unit may be a non-linear equalizer.

    Method and system for digital equalization of a linear or non-linear system
    5.
    发明授权
    Method and system for digital equalization of a linear or non-linear system 有权

    公开(公告)号：US12206426B2

    公开(公告)日：2025-01-21

    申请号：US17358044

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Martin Clara ,  Kameran Azadet

    IPC: H03M1/00 ,  H03M1/06 ,  H03M1/10

    Abstract: A system and method for equalization of a linear or non-linear system. The system includes an adder configured to add an analog reference signal and an input signal, a processing system configured to process a sum of the analog reference signal and the input signal, a non-linear equalizer (NLEQ) configured to process an output of the processing system to remove a distortion incurred by the processing system, a calibration circuitry configured to generate a reconstructed reference signal in digital domain based on measurement of the analog reference signal, and generate coefficients for the NLEQ based on the reconstructed reference signal and the output of the processing system, and a subtractor configured to subtract the reconstructed reference signal from an output of the NLEQ. The analog reference signal may be a sinusoid including single or multiple tones of sinusoids. The non-linear system may be an analog-to-digital converter (ADC).

    CREST FACTOR REDUCTION USING PEAK CANCELLATION WITHOUT PEAK REGROWTH
    8.
    发明公开
    CREST FACTOR REDUCTION USING PEAK CANCELLATION WITHOUT PEAK REGROWTH 审中-公开

    公开(公告)号：US20240004957A1

    公开(公告)日：2024-01-04

    申请号：US17854095

    申请日：2022-06-30

    Applicant: Intel Corporation

    Inventor： Sunitha Motipalli ,  Kameran Azadet ,  Albert Molina ,  Joseph Othmer ,  Kannan Rajamani

    IPC: G06K9/00

    CPC classification number: G06K9/0053 ,  G06K9/0055

    Abstract: Techniques are disclosed for the use of Crest Factor Reduction (CFR) algorithm that performs oversampling of an input signal and a cancellation pulse, and detects a set of peak samples in the upsampled input signal that exceed a predetermined threshold value. The peak samples are clustered such that a subset of the oversampled signal peaks are used to compute gain factors for the generation of a scaled truncated upsampled cancellation pulse. Several scaled truncated upsampled cancellation pulses are applied in parallel to perform peak cancellation of the highest peak in each cluster as part of an initial peak cancellation process. Any remaining peaks are canceled by iterative gain factors computation process. A final cancellation pulse is then generated by multiplying a cancellation pulse by the computed gain factors.

    APPARATUS FOR CALIBRATING A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER
    10.
    发明申请
    APPARATUS FOR CALIBRATING A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER 审中-公开

    公开(公告)号：US20200313687A1

    公开(公告)日：2020-10-01

    申请号：US16799958

    申请日：2020-02-25

    Applicant: Intel Corporation

    Inventor： Matteo Camponeschi ,  Albert Molina

    IPC: H03M1/10 ,  H03M1/12

    Abstract: An apparatus for calibrating a time-interleaved analog-to-digital converter including a plurality of time-interleaved analog-to-digital converter circuits is provided. The apparatus includes a clock generation circuit configured to generate a plurality of phase shifted clock signals for the plurality of time-interleaved analog-to-digital converter circuits and a reference clock signal. Further, the apparatus includes a reference signal generation circuit configured to generate a reference signal based on the reference clock signal. The reference signal is a square wave signal. The apparatus additionally includes a coupling circuit configured to controllably couple an input node of the time-interleaved analog-to-digital converter to either the reference signal generation circuit or to a signal node capable of providing an analog signal for digitization.

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