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公开(公告)号：US10938404B1
公开(公告)日：2021-03-02
申请号：US16728163
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： Ramon Sanchez , Kameran Azadet , Martin Clara , Daniel Gruber
Abstract: A digital-to-analog converter is provided. The digital-to-analog converter comprises an input configured to receiving a first digital control code for controlling a plurality of digital-to-analog converter cells. Further, the digital-to-analog converter comprises a code converter circuit configured to converter the first digital control code to a second digital control code. Further, the digital-to-analog converter comprises a shift code generation circuit configured to generate a shift code based on a code difference between the first digital control code and a third digital control code. The digital-to-analog converter additionally comprises a bit-shifter circuit configured to bit-shift the second digital control code based on the shift code in order to obtain a modified second digital control code. The digital-to-analog converter comprises a cell activation circuit configured to selectively activate one or more of the plurality of digital-to-analog converter cells based on the modified second digital control code. Each activated digital-to-analog converter cell is configured to output a respective cell output signal. Further, the digital-to-analog converter comprises an output configured to output an analog output signal based on the cell output signals.
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公开(公告)号：US11038516B1
公开(公告)日：2021-06-15
申请号：US16886817
申请日：2020-05-29
Applicant: Intel Corporation
Inventor： Kameran Azadet , Ramon Sanchez , Albert Molina , Martin Clara , Daniel Gruber , Matteo Camponeschi
Abstract: An apparatus and method for analog-to-digital conversion. The apparatus includes a first analog-to-digital converter (ADC), a second ADC, and a calibration unit. The first ADC is configured to sample an input analog signal at a first sampling frequency. The second ADC is configured to sample the input analog signal at a second sampling frequency. The second sampling frequency is a fraction of the first sampling frequency. The calibration unit is configured to correct a distortion incurred in an output of the first ADC based on an output of the second ADC. The first ADC may be a time-interleaved ADC. The second ADC may be an extra sub-ADC of the time-interleaved ADC. The second ADC may be configured to sample the input analog signal at random sampling phases. A dithering noise may be added to the input analog signal of the second ADC. The calibration unit may be a non-linear equalizer.
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公开(公告)号：US11171663B2
公开(公告)日：2021-11-09
申请号：US16833729
申请日：2020-03-30
Applicant: Intel Corporation
Inventor： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.
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公开(公告)号：US10715185B1
公开(公告)日：2020-07-14
申请号：US16369317
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
Abstract: A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.
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公开(公告)号：US10608661B1
公开(公告)日：2020-03-31
申请号：US16369262
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.
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Patent Agency Ranking
公开(公告)号：US09262350B2
公开(公告)日：2016-02-16
申请号：US14052911
申请日：2013-10-14
Applicant: Intel Corporation
Inventor： Kannan Rajamani , Ramon Sanchez , Kevin R. Kinney
CPC classification number: G06F13/1647 , H03M13/27 , H04L1/00 , H04L1/0045 , H04L1/0068 , H04L1/0071 , H04L1/1835
Abstract: One embodiment is an apparatus having a memory, a controller, and a de-interleaving module. The memory is configured to store portions of a set of interleaved values, where the set of interleaved values correspond to a single application of an interleaving mapping to a set of un-interleaved values. The controller is configured to retrieve each portion from an other memory that stores the set of interleaved values by moving the portion from the other memory to the memory. The de-interleaving module is configured to de-interleave the interleaved values in at least one of the portions to generate a de-interleaved portion such that processing downstream of the de-interleaving module can begin processing the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved by the de-interleaving module.
Abstract translation: 一个实施例是具有存储器，控制器和解交织模块的装置。 存储器被配置为存储一组交织值的部分，其中交织的值集合对应于一组未交织值的交织映射的单个应用。 控制器被配置为通过将从另一存储器的部分移动到存储器来从存储该组交错值的其他存储器检索每个部分。 解交织模块被配置为对至少一个部分中的交织值进行解交织以产生解交织部分，使得解交织模块的下游处理可以在所有解交织部分之前开始处理去交错部分 交错值组中的交织值由解交织模块进行解交织。
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公开(公告)号：US12034450B2
公开(公告)日：2024-07-09
申请号：US17754308
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
CPC classification number: H03M1/1033 , H03M1/0626
Abstract: An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, is provided. The first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC converter, and the second segment generates a second contribution based on a second number of bits. Further, the apparatus comprises a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits to generate first modified bits, and a second processing circuit comprising a second filter to modify the second number of bits to generate second modified bits. The apparatus additionally comprises an output configured to output a modified digital input word for the DAC, which is based on the first modified bits and the second modified bits.
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公开(公告)号：US11658672B2
公开(公告)日：2023-05-23
申请号：US17455223
申请日：2021-11-17
Applicant: Intel Corporation
Inventor： Ramon Sanchez , Kameran Azadet
IPC: H03M1/10
CPC classification number: H03M1/1052 , H03M1/1061
Abstract: A digital predistortion system and method for pre-distorting an input to a non-linear system. The digital predistortion system includes a digital predistortion circuit and a memory. The digital predistortion circuit is configured to receive input data and modify the input data using at least one look-up table. The at least one look-up table is addressed by a signed real value of the input data. The memory is configured to store the at least one look-up table. The at least one look-up table is implemented based on a generalized memory polynomial model.
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公开(公告)号：US11239866B2
公开(公告)日：2022-02-01
申请号：US16924274
申请日：2020-07-09
Applicant: Intel Corporation
Inventor： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
Abstract: A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.
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公开(公告)号：US10044367B1
公开(公告)日：2018-08-07
申请号：US15671888
申请日：2017-08-08
Applicant: Intel Corporation
Inventor： Kameran Azadet , Ramon Sanchez
Abstract: Techniques for generating signals with arbitrary noise shaping are discussed. One example apparatus configured to be employed within a transmitter can comprise a noise shaper configured to: receive an input signal xq; and apply noise shaping to the input signal xq to generate a noise shaped output signal yq, wherein an in-band noise of the noise shaped output signal yq is below an in-band noise threshold of a spectral mask associated with the noise shaper, wherein an out-of-band noise of the noise shaped output signal yq is below an out-of-band noise threshold of the spectral mask, and wherein a noise of the output signal yq in each of a plurality of bandpass regions is below an associated noise threshold for that bandpass region of the spectral mask.
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