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公开(公告)号：US20200313687A1
公开(公告)日：2020-10-01
申请号：US16799958
申请日：2020-02-25
Applicant: Intel Corporation
Inventor： Matteo Camponeschi , Albert Molina
Abstract: An apparatus for calibrating a time-interleaved analog-to-digital converter including a plurality of time-interleaved analog-to-digital converter circuits is provided. The apparatus includes a clock generation circuit configured to generate a plurality of phase shifted clock signals for the plurality of time-interleaved analog-to-digital converter circuits and a reference clock signal. Further, the apparatus includes a reference signal generation circuit configured to generate a reference signal based on the reference clock signal. The reference signal is a square wave signal. The apparatus additionally includes a coupling circuit configured to controllably couple an input node of the time-interleaved analog-to-digital converter to either the reference signal generation circuit or to a signal node capable of providing an analog signal for digitization.
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公开(公告)号：US11038516B1
公开(公告)日：2021-06-15
申请号：US16886817
申请日：2020-05-29
Applicant: Intel Corporation
Inventor： Kameran Azadet , Ramon Sanchez , Albert Molina , Martin Clara , Daniel Gruber , Matteo Camponeschi
Abstract: An apparatus and method for analog-to-digital conversion. The apparatus includes a first analog-to-digital converter (ADC), a second ADC, and a calibration unit. The first ADC is configured to sample an input analog signal at a first sampling frequency. The second ADC is configured to sample the input analog signal at a second sampling frequency. The second sampling frequency is a fraction of the first sampling frequency. The calibration unit is configured to correct a distortion incurred in an output of the first ADC based on an output of the second ADC. The first ADC may be a time-interleaved ADC. The second ADC may be an extra sub-ADC of the time-interleaved ADC. The second ADC may be configured to sample the input analog signal at random sampling phases. A dithering noise may be added to the input analog signal of the second ADC. The calibration unit may be a non-linear equalizer.
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公开(公告)号：US12015417B2
公开(公告)日：2024-06-18
申请号：US17131868
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Daniel Gruber , Matteo Camponeschi , Christian Lindholm , Martin Clara , Giacomo Cascio
CPC classification number: H03M1/0609 , H03K3/02 , H04B1/16
Abstract: An input buffer circuit for an analog-to-digital converter is provided. The input buffer circuit includes a buffer amplifier. The buffer amplifier includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair for the analog-to-digital converter. The buffer amplifier further includes a first output node and a second output node each configured to output a respective one of a first buffered signal and a second buffered signal. In addition, the input buffer circuit includes feedback circuitry. The feedback circuitry is configured to generate, based on the first buffered signal and the second buffered signal, a first feedback signal and a second feedback signal for mitigating a respective unwanted signal component at the first input node and the second input node related to a limited reverse isolation of the amplifier buffer. The feedback circuitry is further configured to supply the first feedback signal to the first input node and the second feedback signal to the second input node.
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公开(公告)号：US12003248B2
公开(公告)日：2024-06-04
申请号：US17131819
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Matteo Camponeschi , Albert Molina , Kannan Rajamani , Giacomo Cascio , Christian Lindholm
CPC classification number: H03M1/1009 , H04B1/40 , H04L5/0048
Abstract: A method and system for controlling an analog-to-digital converter (ADC) in an observation path in a transceiver. The transceiver includes a transmit path, a receive path, and an observation path. The observation path includes an analog buffer and an observation ADC. A controller generates a control signal to control sampling events at the observation ADC to activate the observation ADC at combined uniform and non-uniform sampling instants. The controller may also generate a second control signal indicating whether digital data obtained by the observation ADC is valid or not. The digital data generated by the observation ADC at non-uniform sampling instants is indicated as invalid and digital data generated by the observation ADC at uniform sampling instants is indicated as valid. The digital data indicated as invalid may be discarded and the digital data indicated as valid is used for calibration of the transmit path or the receive path.
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公开(公告)号：US11271578B2
公开(公告)日：2022-03-08
申请号：US17059495
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Albert Molina , Kameran Azadet , Matteo Camponeschi , Jose Luis Ceballos , Christian Lindholm
Abstract: A time-interleaved Analog-to-Digital Converter, ADC, system is provided. The time-inter-leaved ADC system includes time-interleaved first and second ADC circuits and a switching circuit. The switching circuit is configured to selectively supply an analog input signal for digitization to at least one of the first ADC circuit, the second ADC circuit or ground, and to selectively supply an analog calibration signal to at least one of the first ADC circuit, the second ADC circuit or ground. Further, the time-interleaved ADC system includes an output circuit configured to selectively generate, based on least one of a first digital signal output by the first ADC circuit and a second digital signal output by the second ADC circuit, a digital output signal.
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Patent Agency Ranking
公开(公告)号：US10601434B1
公开(公告)日：2020-03-24
申请号：US16369237
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Albert Molina , Kameran Azadet , Matteo Camponeschi , Jose Luis Ceballos , Christian Lindholm , Hundo Shin , Martin Clara
Abstract: An apparatus for calibrating a time-interleaved analog-to-digital converter including a plurality of time-interleaved analog-to-digital converter circuits is provided. The apparatus includes an analog signal generation circuit configured to generate an analog calibration signal based on a digital calibration signal representing one or more digital data sequences for calibration. The analog calibration signal is a wideband signal. Further, the apparatus includes a coupling circuit configured to controllably couple an input node of the time-interleaved analog-to-digital converter to either the analog signal generation circuit or to a node capable of providing an analog signal for digitization.
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公开(公告)号：US12063050B2
公开(公告)日：2024-08-13
申请号：US17754309
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： Albert Molina , Kameran Azadet , Martin Clara , Matteo Camponeschi , Christian Lindholm
CPC classification number: H03M1/466
Abstract: An analog-to-digital converter comprising a plurality of sampling cells. At least one of the plurality of sampling cells comprises a capacitive element coupled to a cell output of the at least one of the plurality of sampling cells, wherein a cell output signal is provided at the cell output. The at least one of the plurality of sampling cells further comprises a first cell input for receiving an input signal to be digitized, and a second cell input for receiving a calibration signal. Additionally, the at least one of the plurality of sampling cells comprises a first switch circuit capable of selectively coupling the first cell input to the capacitive element based on a clock signal, and a second switch circuit capable of selectively coupling the second cell input to the capacitive element, wherein a size of the second switch circuit is smaller than a size of the first switch circuit.
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公开(公告)号：US11996814B2
公开(公告)日：2024-05-28
申请号：US17059491
申请日：2019-08-05
Applicant: Intel Corporation
Inventor： Matteo Camponeschi , Lukas Doerrer , Patrick Torta
CPC classification number: H03H11/1286 , H03H7/38 , H03M3/424 , H03M3/438 , H03M3/458
Abstract: An active filter and an analog-to-digital converter (ADC) configured to suppress out-of-band peaking. An active filter may include an active device configured to provide a power gain to an input signal, a feedback network configured to connect an output of the active device to an input of the active device, and an input impedance network configured to couple the input signal to the input of the active device. A combination of the feedback network and the input impedance network is configured to provide frequency response properties of the active filter such that a frequency domain signal transfer function of the active filter has a constant in numerator.
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公开(公告)号：US11177820B2
公开(公告)日：2021-11-16
申请号：US16933292
申请日：2020-07-20
Applicant: Intel Corporation
Inventor： Albert Molina , Martin Clara , Matteo Camponeschi , Christian Lindholm , Kameran Azadet
Abstract: A n-bit Successive Approximation Register Analog-to-Digital Converter, SAR ADC, is provided. The SAR ADC comprises a respective plurality of sampling cells for each bit of the n-bit of the SAR ADC. Each sampling cell comprises a capacitive element coupled to a cell output of the sampling cell in order to provide a cell output signal. Further, each sampling cell comprises a first cell input for receiving a first signal, and a first switch circuit capable of selectively coupling the first cell input to the capacitive element. Each cell additionally comprises a second cell input for receiving a second signal, and a third cell input for receiving a third signal. The third signal exhibits opposite polarity compared to the second signal. Each sampling cell comprises a second switch circuit capable of selectively coupling one of the second cell input and the third cell input to the capacitive element. The SAR ADC further comprises at least one comparator circuit coupled to the sampling cells. The at least one comparator circuit is configured to output a comparison signal based on the cell output signals of the sampling cells. Additionally, the SAR ADC comprises a calibration circuit configured to supply at least one respective control signal to the respective second switch circuit of the sampling cells for controlling the second switch circuits.
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公开(公告)号：US10958280B2
公开(公告)日：2021-03-23
申请号：US16788338
申请日：2020-02-12
Applicant: Intel Corporation
Inventor： Matteo Camponeschi , Christian Lindholm
Abstract: An apparatus for calibrating an analog-to-digital converter is provided. The apparatus includes a reference input generation circuit configured to subsequently generate two reference inputs for calibrating the analog-to-digital converter. The two reference inputs both represent ramp waveforms, wherein the ramp waveforms represented by the two reference inputs are different from each other. Further, the apparatus includes a coupling circuit configured to controllably couple an input node of the analog-to-digital converter to either the reference input generation circuit or to a signal node capable of providing an analog input for digitization.
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