公开(公告)号：US20160358886A1

公开(公告)日：2016-12-08

申请号：US15171364

申请日：2016-06-02

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Edward Fuergut ,  Joachim Mahler

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L23/44 ,  H01L23/13 ,  H01L23/5385 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/071 ,  H01L2224/291 ,  H01L2224/32227 ,  H01L2224/3701 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40228 ,  H01L2224/40499 ,  H01L2224/41051 ,  H01L2224/4118 ,  H01L2224/831 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/848 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/9201 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/15151 ,  H01L2924/15153 ,  H05K7/023 ,  H05K7/08 ,  H05K7/10 ,  H05K7/20 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83

Abstract: A semiconductor power arrangement includes a chip carrier having a first surface and a second surface opposite the first surface. The semiconductor power arrangement further includes a plurality of power semiconductor chips attached to the chip carrier, wherein the power semiconductor chips are inclined to the first and/or second surface of the chip carrier.

Abstract translation: 半导体功率装置包括具有第一表面和与第一表面相对的第二表面的芯片载体。 半导体功率布置还包括附接到芯片载体的多个功率半导体芯片，其中功率半导体芯片倾斜于芯片载体的第一和/或第二表面。

公开(公告)号：US09425116B2

公开(公告)日：2016-08-23

申请号：US13656822

申请日：2012-10-22

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Frank Daeche

IPC: H01L23/12 ,  H01L21/52 ,  H01L23/50 ,  H01L23/13 ,  H05K1/18 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H05K3/46

CPC classification number: H01L23/12 ,  H01L21/52 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/24101 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/82106 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/1431 ,  H01L2924/15153 ,  H01L2924/15311 ,  H05K1/186 ,  H05K3/4697 ,  H01L2924/00

Abstract: An integrated circuit package includes a package module including one or more circuit interconnections formed in a carrier, wherein at least one top-side package contact is formed over the top-side of the package module and electrically connected to at least one circuit interconnection of the one or more circuit interconnections and wherein a cavity is formed at the top-side of the package module; a chip disposed in the cavity, the chip including at least one chip front side contact and at least one chip back side contact, wherein the at least one chip front side contact is electrically connected to at least one further circuit interconnection of the one or more circuit interconnections; an electrically conductive structure connecting the at least one top-side package contact to the chip back side contact; and a metallic layer formed over the electrically conductive structure and on the chip back side contact.

Abstract translation: 集成电路封装包括封装模块，该封装模块包括形成在载体中的一个或多个电路互连，其中至少一个顶侧封装触点形成在封装模块的顶侧之上，并电连接到封装模块的至少一个电路互连 一个或多个电路互连，并且其中空腔形成在封装模块的顶侧; 设置在所述空腔中的芯片，所述芯片包括至少一个芯片前侧触点和至少一个芯片背面接触件，其中所述至少一个芯片前侧触点电连接到所述一个或多个芯片前侧触点的至少一个另外的电路互连 电路互连; 将所述至少一个顶侧封装触头连接到所述芯片背侧触点的导电结构; 以及形成在导电结构上和芯片背侧接触件上的金属层。

公开(公告)号：US09331019B2

公开(公告)日：2016-05-03

申请号：US13689511

申请日：2012-11-29

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Reinhard Pufall

IPC: H01L23/48 ,  H01L23/532 ,  G01R31/26 ,  G01R31/28 ,  H01L23/58 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L22/32 ,  G01R31/26 ,  G01R31/28 ,  G01R31/2853 ,  G01R31/2884 ,  H01L21/7685 ,  H01L21/76868 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53204 ,  H01L23/58 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05556 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and the ductile layer.

Abstract translation: 公开了包括延展层的装置，用于制造包括延展层的部件的方法和用于测试部件的方法。 实施例包括在第一导电层和延性层之间包括第一导电层，延性层和脆性层的电子器件。

公开(公告)号：US09190389B2

公开(公告)日：2015-11-17

申请号：US13951554

申请日：2013-07-26

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Joachim Mahler ,  Khalil Hosseini

IPC: H01L23/02 ,  H01L25/04 ,  H01L23/00 ,  H01L23/498 ,  H01L25/16 ,  H01L23/538

CPC classification number: H01L25/04 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

Abstract: A chip package device includes an electrically conducting chip carrier, at least one semiconductor chip attached to the electrically conducting chip carrier, and an insulating laminate structure embedding the chip carrier, the at least one semiconductor chip and a passive electronic device. The passive electronic device includes a first structured electrically conducting layer, the first structured electrically conducting layer extending over a surface of the laminate structure.

Abstract translation: 芯片封装器件包括导电芯片载体，至少一个连接到导电芯片载体的半导体芯片，以及嵌入芯片载体，至少一个半导体芯片和无源电子器件的绝缘叠层结构。 无源电子器件包括第一结构导电层，第一结构化导电层在层压结构的表面上延伸。

公开(公告)号：US20150155267A1

公开(公告)日：2015-06-04

申请号：US14096063

申请日：2013-12-04

Applicant: Infineon Technologies AG

Inventor： Juergen HOEGERL ,  Georg Meyer-Berg

IPC: H01L25/065 ,  H01L23/367 ,  H01L21/78 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/492 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49844 ,  H01L24/03 ,  H01L24/06 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/04042 ,  H01L2224/05024 ,  H01L2224/37147 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electronic component comprising an electrically conductive chip carrier comprising an electrically insulating core structure at least partially covered with electrically conductive material, at least one electronic chip each having a first main surface attached to the chip carrier, and a sheet-like redistribution structure attached to a second main surface of the at least one electronic chip and configured for electrically connecting the second main surface of the at least one electronic chip with the chip carrier.

Abstract translation: 一种电子部件，包括导电芯片载体，其包括至少部分地被导电材料覆盖的电绝缘芯结构，至少一个电子芯片，每个电子芯片具有附接到芯片载体的第一主表面，以及片状再分布结构， 所述至少一个电子芯片的第二主表面被配置为将所述至少一个电子芯片的第二主表面与所述芯片载体电连接。

公开(公告)号：US09041226B2

公开(公告)日：2015-05-26

申请号：US13798141

申请日：2013-03-13

Applicant: Infineon Technologies AG

Inventor： Rainer Steiner ,  Edward Fuergut ,  Khalil Hosseini ,  Georg Meyer-Berg ,  Joachim Mahler

IPC: H01L23/48 ,  H01L21/00 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/24 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/24246 ,  H01L2224/2518 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/07802 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

Abstract: In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.

Abstract translation: 在各种实施例中，提供了芯片布置。 芯片布置可以包括芯片载体和安装在芯片载体上的芯片。 芯片可以包括至少两个芯片触点和芯片与芯片载体之间的绝缘粘合剂，以将芯片粘附到芯片载体上。 所述至少两个芯片触点可以电耦合到芯片载体。

公开(公告)号：US20150049443A1

公开(公告)日：2015-02-19

申请号：US13965246

申请日：2013-08-13

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg

IPC: H05K1/18

CPC classification number: H05K1/189 ,  H01L23/49833 ,  H01L23/4985 ,  H01L23/5383 ,  H01L23/5387 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K1/0209 ,  H05K1/0271 ,  H05K1/141 ,  H05K1/145 ,  H05K3/32 ,  H05K3/361 ,  H05K2201/05 ,  H05K2201/10378 ,  H05K2201/105 ,  H05K2201/1053 ,  H05K2201/10659 ,  H05K2201/10704 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10954 ,  H05K2201/10962 ,  H01L2924/00

Abstract: According to various embodiments, a chip arrangement may be provided, the chip arrangement may include: a first carrier; at least one chip arranged over the first carrier; a flexible structure including a wiring layer structure; and a contact structure arranged between the first carrier and the wiring layer structure, wherein the at least one chip is electrically coupled to the first carrier via the wiring layer structure and the contact structure.

Abstract translation: 根据各种实施例，可以提供芯片布置，芯片布置可以包括：第一载体; 布置在所述第一载体上的至少一个芯片; 包括布线层结构的柔性结构; 以及布置在所述第一载体和所述布线层结构之间的接触结构，其中所述至少一个芯片经由所述布线层结构和所述接触结构电耦合到所述第一载体。

公开(公告)号：US20130122660A1

公开(公告)日：2013-05-16

申请号：US13733375

申请日：2013-01-03

Applicant: Infineon Technologies AG

Inventor： Klaus Elian ,  Georg Meyer-Berg ,  Horst Theuss

IPC: H01L21/56

CPC classification number: H01L21/563 ,  G01L9/0054 ,  G01L19/0627 ,  G01L19/141 ,  G01L19/147 ,  G01L19/148 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/1461 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A sensor device and method. One embodiment provides a first semiconductor chip having a sensing region. A porous structure element is attached to the first semiconductor chip. A first region of the porous structure element faces the sensing region of the first semiconductor chip. An encapsulation material partially encapsulates the first semiconductor chip and the porous structure element.

Abstract translation: 传感器装置及方法。 一个实施例提供了具有感测区域的第一半导体芯片。 多孔结构元件附接到第一半导体芯片。 多孔结构元件的第一区域面向第一半导体芯片的感测区域。 封装材料部分地封装第一半导体芯片和多孔结构元件。

公开(公告)号：US20130082386A1

公开(公告)日：2013-04-04

申请号：US13656822

申请日：2012-10-22

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Frank Daeche

IPC: H01L23/12 ,  H01L23/50 ,  H01L21/52

CPC classification number: H01L23/12 ,  H01L21/52 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/24101 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/82106 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/1431 ,  H01L2924/15153 ,  H01L2924/15311 ,  H05K1/186 ,  H05K3/4697 ,  H01L2924/00

Abstract: An integrated circuit package includes a package module including one or more circuit interconnections formed in a carrier, wherein at least one top-side package contact is formed over the top-side of the package module and electrically connected to at least one circuit interconnection of the one or more circuit interconnections and wherein a cavity is formed at the top-side of the package module; a chip disposed in the cavity, the chip including at least one chip front side contact and at least one chip back side contact, wherein the at least one chip front side contact is electrically connected to at least one further circuit interconnection of the one or more circuit interconnections; an electrically conductive structure connecting the at least one top-side package contact to the chip back side contact; and a metallic layer formed over the electrically conductive structure and on the chip back side contact.

Abstract translation: 集成电路封装包括封装模块，该封装模块包括形成在载体中的一个或多个电路互连，其中至少一个顶侧封装触点形成在封装模块的顶侧之上，并电连接到封装模块的至少一个电路互连 一个或多个电路互连，并且其中空腔形成在封装模块的顶侧; 设置在所述空腔中的芯片，所述芯片包括至少一个芯片前侧触点和至少一个芯片背面接触件，其中所述至少一个芯片前侧触点电连接到所述一个或多个芯片前侧触点的至少一个另外的电路互连 电路互连; 将所述至少一个顶侧封装触头连接到所述芯片背侧触点的导电结构; 以及形成在导电结构上和芯片背侧接触件上的金属层。

公开(公告)号：US11195787B2

公开(公告)日：2021-12-07

申请号：US15045687

申请日：2016-02-17

Applicant: Infineon Technologies AG

Inventor： Ngoc-Hoa Huynh ,  Franz-Xaver Muehlbauer ,  Claus Waechter ,  Veronika Huber ,  Dominic Maier ,  Thomas Kilger ,  Saverio Trotta ,  Ashutosh Baheti ,  Georg Meyer-Berg ,  Maciej Wojnowski

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/367 ,  H01L23/538 ,  H01Q9/28 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q21/06 ,  H01L21/56 ,  H01Q9/26

Abstract: A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.