公开(公告)号：US09331019B2

公开(公告)日：2016-05-03

申请号：US13689511

申请日：2012-11-29

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Reinhard Pufall

IPC: H01L23/48 ,  H01L23/532 ,  G01R31/26 ,  G01R31/28 ,  H01L23/58 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L22/32 ,  G01R31/26 ,  G01R31/28 ,  G01R31/2853 ,  G01R31/2884 ,  H01L21/7685 ,  H01L21/76868 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53204 ,  H01L23/58 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05556 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and the ductile layer.

Abstract translation: 公开了包括延展层的装置，用于制造包括延展层的部件的方法和用于测试部件的方法。 实施例包括在第一导电层和延性层之间包括第一导电层，延性层和脆性层的电子器件。

公开(公告)号：US20220270985A1

公开(公告)日：2022-08-25

申请号：US17582285

申请日：2022-01-24

Applicant: Infineon Technologies AG

Inventor： Sergey Ananiev ,  Andreas Bauer ,  Michael Goroll ,  Maria Heidenblut ,  Stefan Kaiser ,  Gunther Mackh ,  Kabula Mutamba ,  Reinhard Pufall ,  Georg Reuther

IPC: H01L23/00

Abstract: A semiconductor chip having a crack stop structure is disclosed. The crack stop structure includes one or more recesses formed in the semiconductor chip. The one or more recesses extend adjacent to and along a periphery of the semiconductor chip. The one or more recesses are filled with a metal material. The metal material has an intrinsic tensile stress at room temperature that induces compressive stress in at least a region of the periphery of the semiconductor chip.

公开(公告)号：US10734352B2

公开(公告)日：2020-08-04

申请号：US16148316

申请日：2018-10-01

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Khalil Hosseini ,  Johannes Lodermeyer ,  Joachim Mahler ,  Thorsten Meyer ,  Georg Meyer-Berg ,  Ivan Nikitin ,  Reinhard Pufall ,  Edmund Riedl ,  Klaus Schmidt ,  Manfred Schneegans ,  Patrick Schwarz

IPC: H01L23/00

Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

公开(公告)号：US20190103378A1

公开(公告)日：2019-04-04

申请号：US16148316

申请日：2018-10-01

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Khalil Hosseini ,  Johannes Lodermeyer ,  Joachim Mahler ,  Thorsten Meyer ,  Georg Meyer-Berg ,  Ivan Nikitin ,  Reinhard Pufall ,  Edmund Riedl ,  Klaus Schmidt ,  Manfred Schneegans ,  Patrick Schwarz

IPC: H01L23/00

Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

公开(公告)号：US10090216B2

公开(公告)日：2018-10-02

申请号：US15442084

申请日：2017-02-24

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Reinhard Pufall ,  Michael Goroll ,  Rainer Dudek

IPC: H01L23/04 ,  H05K1/18 ,  H01L25/10

Abstract: A semiconductor package includes a block having opposing first and second main surfaces and sides between the first and second main surfaces, and an encapsulation material at least partly covering the block. One or both of the main surfaces of the block has recessed regions. The recessed regions do not extend completely through the block from one main surface to the other main surface. The encapsulation material fills the recessed regions to form an interlocked connection between the block and the encapsulation material. Additional semiconductor package embodiments are provided.

公开(公告)号：US20170170082A1

公开(公告)日：2017-06-15

申请号：US15442084

申请日：2017-02-24

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Reinhard Pufall ,  Michael Goroll ,  Rainer Dudek

IPC: H01L23/04 ,  H01L25/10 ,  H05K1/18

CPC classification number: H01L23/04 ,  G06F17/5068 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49811 ,  H01L24/81 ,  H01L25/10 ,  H01L2224/01 ,  H01L2224/291 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/83447 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/35121 ,  H05K1/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor package includes a block having opposing first and second main surfaces and sides between the first and second main surfaces, and an encapsulation material at least partly covering the block. One or both of the main surfaces of the block has recessed regions. The recessed regions do not extend completely through the block from one main surface to the other main surface. The encapsulation material fills the recessed regions to form an interlocked connection between the block and the encapsulation material. Additional semiconductor package embodiments are provided.

公开(公告)号：US09576867B2

公开(公告)日：2017-02-21

申请号：US15093528

申请日：2016-04-07

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Reinhard Pufall

IPC: H01L23/48 ,  H01L21/66 ,  G01R31/26 ,  G01R31/28 ,  H01L23/58 ,  H01L21/768 ,  H01L23/532 ,  H01L23/00 ,  H01L23/522 ,  H01L23/525

CPC classification number: H01L22/32 ,  G01R31/26 ,  G01R31/28 ,  G01R31/2853 ,  G01R31/2884 ,  H01L21/7685 ,  H01L21/76868 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53204 ,  H01L23/58 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05556 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and the ductile layer.

Abstract translation: 公开了包括延展层的装置，用于制造包括延展层的部件的方法和用于测试部件的方法。 实施例包括在第一导电层和延性层之间包括第一导电层，延性层和脆性层的电子器件。

公开(公告)号：US20140145333A1

公开(公告)日：2014-05-29

申请号：US13689511

申请日：2012-11-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Georg Meyer-Berg ,  Reinhard Pufall

IPC: H01L23/532 ,  G01R31/26 ,  H01L21/768

CPC classification number: H01L22/32 ,  G01R31/26 ,  G01R31/28 ,  G01R31/2853 ,  G01R31/2884 ,  H01L21/7685 ,  H01L21/76868 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53204 ,  H01L23/58 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05556 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and the ductile layer.

Abstract translation: 公开了包括延展层的装置，用于制造包括延展层的部件的方法和用于测试部件的方法。 实施例包括在第一导电层和延性层之间包括第一导电层，延性层和脆性层的电子器件。

公开(公告)号：US09627305B2

公开(公告)日：2017-04-18

申请号：US13939248

申请日：2013-07-11

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Reinhard Pufall ,  Michael Goroll ,  Rainer Dudek

IPC: H01L23/498 ,  G06F17/50 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/04 ,  G06F17/5068 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49811 ,  H01L24/81 ,  H01L25/10 ,  H01L2224/01 ,  H01L2224/291 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/83447 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/35121 ,  H05K1/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor package includes a support substrate having opposing first and second main surfaces and sides between the first and second main surfaces, a semiconductor die attached to one of the main surfaces of the support substrate, and an encapsulation material at least partly covering the support substrate and the semiconductor die. A protrusion extends outward from a side of the support substrate and terminates in the encapsulation material. The protrusion forms an interlocked connection with the encapsulation material. The interlocked connection increases the tensile strength of the interface between the encapsulation material and the side of the support substrate with the protrusion.

公开(公告)号：US20160218044A1

公开(公告)日：2016-07-28

申请号：US15093528

申请日：2016-04-07

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Reinhard Pufall

IPC: H01L21/66 ,  H01L23/525 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L22/32 ,  G01R31/26 ,  G01R31/28 ,  G01R31/2853 ,  G01R31/2884 ,  H01L21/7685 ,  H01L21/76868 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53204 ,  H01L23/58 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05556 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and the ductile layer.

Abstract translation: 公开了包括延展层的装置，用于制造包括延展层的部件的方法和用于测试部件的方法。 实施例包括在第一导电层和延性层之间包括第一导电层，延性层和脆性层的电子器件。