公开(公告)号：US11830824B2

公开(公告)日：2023-11-28

申请号：US17214411

申请日：2021-03-26

Applicant: Applied Materials, Inc.

Inventor： Amirhasan Nourbakhsh ,  Lan Yu ,  Joseph F. Salfelder ,  Ki Cheol Ahn ,  Tyler Sherwood ,  Siddarth Krishnan ,  Michael Jason Fronckowiak ,  Xing Chen

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L23/562 ,  H01L21/304 ,  H01L21/3086 ,  H01L21/31111

Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.

公开(公告)号：US11769665B2

公开(公告)日：2023-09-26

申请号：US17572963

申请日：2022-01-11

Applicant: Applied Materials, Inc.

Inventor： Amirhasan Nourbakhsh ,  Raman Gaire ,  Tyler Sherwood ,  Lan Yu ,  Roger Quon ,  Siddarth Krishnan

IPC: H01L21/02

CPC classification number: H01L21/02576 ,  H01L21/02532 ,  H01L21/02579

Abstract: Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.

公开(公告)号：US11456171B2

公开(公告)日：2022-09-27

申请号：US16953577

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Tyler Sherwood

IPC: H01L21/02 ,  H01L29/06 ,  H01L21/762

Abstract: Exemplary methods of forming a semiconductor structure may include forming a liner along sidewalls of a trench defined from a first surface of a semiconductor substrate. The liner may extend along the first surface of the semiconductor substrate. The methods may include filling the trench with a dielectric material. The methods may include removing the dielectric material and the liner from the first surface of the semiconductor substrate. The methods may include forming a layer of the liner across the first surface of the semiconductor substrate and the trench defined within the semiconductor substrate.

公开(公告)号：US11881539B2

公开(公告)日：2024-01-23

申请号：US17100402

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: H01L33/00 ,  H01L33/62 ,  G02F1/1362

CPC classification number: H01L33/0095 ,  G02F1/136277 ,  H01L33/62 ,  H01L2933/0066

Abstract: Processing methods may be performed to form a pixel material in a semiconductor substrate. The methods may include forming a lithographic mask overlying the semiconductor substrate. The lithographic mask may include a window. The method may include forming a via in the semiconductor substrate by a dry etch process through the window. The method may also include forming the pixel material by depositing a fill material in the via.

公开(公告)号：US20230223256A1

公开(公告)日：2023-07-13

申请号：US17572963

申请日：2022-01-11

Applicant: Applied Materials, Inc.

Inventor： Amirhasan Nourbakhsh ,  Raman Gaire ,  Tyler Sherwood ,  Lan Yu ,  Roger Quon ,  Siddarth Krishnan

IPC: H01L21/02

CPC classification number: H01L21/02576 ,  H01L21/02579 ,  H01L21/02532

Abstract: Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.

公开(公告)号：US20220285584A1

公开(公告)日：2022-09-08

申请号：US17195271

申请日：2021-03-08

Applicant: Applied Materials, Inc.

Inventor： Michel Khoury ,  Lan Yu ,  Michael Chudzik ,  Max Batres

IPC: H01L33/32 ,  H01L33/00 ,  H01L33/46 ,  H01L33/58

Abstract: Exemplary processing methods of forming a semiconductor structure may include forming subpixels on a substrate. Each of the subpixels may include a gallium-and-nitrogen-containing layer formed on an exposed portion of a nucleation layer on the substrate. The subpixels may further include a porosified region formed on or in the gallium-and-nitrogen-containing region, and an active region formed on the porosified region. The active region may include an indium-gallium-and-nitrogen-containing material. The processing methods may further include forming a first reflection layer around one of the subpixels, wherein the first reflection layer includes a first metal layer. The methods may additionally include forming a second reflection layer around another of the subpixels, wherein the second reflection layer includes a second metal that is different than the first metal.

公开(公告)号：US20220254886A1

公开(公告)日：2022-08-11

申请号：US17169916

申请日：2021-02-08

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  El Mehdi Bazizi ,  Siddarth Krishnan ,  Xing Chen ,  Lan Yu ,  Tyler Sherwood

IPC: H01L29/36 ,  H01L29/872 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/3065 ,  H01L29/66

Abstract: Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 μm. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.

公开(公告)号：US20220165610A1

公开(公告)日：2022-05-26

申请号：US16953567

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Tyler Sherwood ,  Michael Chudzik ,  Siddarth Krishnan

IPC: H01L21/768 ,  H01L21/762 ,  H01L29/06

Abstract: Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.

公开(公告)号：US20220163846A1

公开(公告)日：2022-05-26

申请号：US17100422

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: G02F1/1335 ,  H01L21/768 ,  G02F1/1362 ,  H01L23/522

Abstract: Processing methods may be performed to forming a pixel material in a semiconductor structure. The methods may include forming a sacrificial hardmask overlying an uppermost layer of an optical stack of the semiconductor structure, the uppermost layer having a thickness. The methods may include forming a via through the sacrificial hardmask in the optical stack by a first etch process unselective to a metal layer of the semiconductor structure. The methods may include filling the via with a fill material, wherein a portion of the fill material extends over the sacrificial hardmask and contacts the metal layer. The methods may include removing a portion of the fill material external to the via by a removal process selective to the fill material. The methods may also include removing the sacrificial hardmask by a second etch process selective to the sacrificial hardmask while maintaining the thickness of the uppermost layer.

公开(公告)号：US20240154018A1

公开(公告)日：2024-05-09

申请号：US18411693

申请日：2024-01-12

Applicant: Applied Materials, Inc.

Inventor： Ria Someshwar ,  Seshadri Ganguli ,  Lan Yu ,  Siddarth Krishnan ,  Srinivas Gandikota ,  Jacqueline S. Wrench ,  Yixiong Yang

IPC: H01L29/45 ,  H01L21/285 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/456 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/401 ,  H01L29/45 ,  H01L29/665

Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.