知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

76 records (took 0.026 seconds)

    INTEGRATED DIPOLE REGION FOR TRANSISTOR
    1.
    发明申请
    INTEGRATED DIPOLE REGION FOR TRANSISTOR 有权

    公开(公告)号：US20250006499A1

    公开(公告)日：2025-01-02

    申请号：US18823999

    申请日：2024-09-04

    Applicant: Applied Materials, Inc.

    Inventor： Srinivas Gandikota ,  Yixiong Yang ,  Steven C.H. Hung ,  Tianyi Huang ,  Seshadri Ganguli

    IPC: H01L21/28 ,  H01L21/324 ,  H01L21/8238

    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-κ dielectric layer on the metal film. In some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-κ dielectric layer on the interfacial layer, and a metal film on the high-κ dielectric layer. In some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-κ dielectric layer.

    CONFORMAL MOLYBDENUM DEPOSITION
    3.
    发明公开
    CONFORMAL MOLYBDENUM DEPOSITION 审中-公开

    公开(公告)号：US20240026529A1

    公开(公告)日：2024-01-25

    申请号：US18222589

    申请日：2023-07-17

    Applicant: Applied Materials, Inc.

    Inventor： Srinivas Gandikota ,  Tuerxun Ailihumaer ,  Yixiong Yang ,  Seshadri Ganguli ,  Yogesh Sharma

    IPC: C23C16/08 ,  C23C16/02 ,  C23C16/04

    CPC classification number: C23C16/08 ,  C23C16/0272 ,  C23C16/045

    Abstract: Embodiments of the disclosure provide conformally deposited molybdenum films having reduced resistivity and methods of forming the same. The methods include converting an amorphous silicon layer to a metal layer by thermally soaking the amorphous silicon layer comprising silicon atoms in the presence of a metal compound selected from the group consisting of a molybdenum compound and a tungsten compound until at least a portion of the silicon atoms in the amorphous silicon layer are replaced by metal atoms selected from the group consisting of molybdenum atoms and tungsten atoms. The methods include conformally depositing a molybdenum film on the metal layer.

    Selective cobalt deposition on copper surfaces
    7.
    发明授权
    Selective cobalt deposition on copper surfaces 有权

    公开(公告)号：US11384429B2

    公开(公告)日：2022-07-12

    申请号：US15598687

    申请日：2017-05-18

    Applicant: Applied Materials, Inc.

    Inventor： Sang-Ho Yu ,  Kevin Moraes ,  Seshadri Ganguli ,  Hua Chung ,  See-Eng Phan

    IPC: C23C16/16 ,  H01L21/324 ,  H01L21/768 ,  C23C16/02 ,  C23C16/18 ,  H01L21/02 ,  H01L21/285 ,  C23C16/455 ,  C23C16/50

    Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface. In another embodiment, a deposition-treatment cycle includes performing the vapor deposition process and subsequently a post-treatment process, which deposition-treatment cycle may be repeated to form multiple cobalt capping layers.

    CATALYST ENHANCED SEAMLESS RUTHENIUM GAP FILL
    9.
    发明申请
    CATALYST ENHANCED SEAMLESS RUTHENIUM GAP FILL 有权

    公开(公告)号：US20210214842A1

    公开(公告)日：2021-07-15

    申请号：US17140419

    申请日：2021-01-04

    Applicant: Applied Materials, Inc.

    Inventor： Byunghoon Yoon ,  Seshadri Ganguli ,  Xi Cen

    IPC: C23C16/02 ,  C23C16/04 ,  C23C16/18 ,  C23C16/455 ,  H01L21/768

    Abstract: Methods of depositing a metal film with high purity are discussed. A catalyst enhanced CVD process is utilized comprising an alkyl halide catalyst soak and a precursor exposure. The precursor comprises a metal precursor having the general formula (I): M-L1(L2)y, wherein M is a metal, L1 is an aromatic ligand, L2 is an aliphatic ligand, and y is a number in the range of from 2 to 8 to form a metal film on the substrate surface, wherein the L2 comprises 1,5-hexdiene, 1,4-hexadiene, and less than 5% of 1,3-hexadiene. Selective deposition of a metal film with high purity on a metal surface over a dielectric surface is described.

Patent Agency Ranking