公开(公告)号：US20250126867A1

公开(公告)日：2025-04-17

申请号：US18379928

申请日：2023-10-13

Applicant: Applied Materials, Inc.

Inventor： Srinivas Gandikota ,  Yixiong Yang ,  Seshadri Ganguli ,  Geetika Bajaj ,  Debaditya Chatterjee ,  Hsin-Jung Yu ,  Tuerxun Ailihumaer ,  Tengzhou Ma ,  Lin Sun

IPC: H01L29/40 ,  H01L21/324 ,  H01L29/49 ,  H01L29/51

Abstract: Methods of scaling the thickness of the interfacial layer in electronic devices, such as NMOS transistors and PMOS transistors are described. Some embodiments provide a metal film or a metal nitride film that reduces the thickness of the interfacial layer by scavenging unbound oxygen from the interfacial layer (e.g., silicon oxide (SiOx)) and the high-κ dielectric layer (e.g., hafnium oxide (HfOx)). Some embodiments advantageously include annealing the semiconductor substrate to promote or accelerate the scavenging.

公开(公告)号：US20240360557A1

公开(公告)日：2024-10-31

申请号：US18139121

申请日：2023-04-25

Applicant: Applied Materials, Inc.

Inventor： Srinivas Gandikota ,  Yixiong Yang ,  Tianyi Huang ,  Geetika Bajaj ,  Hsin-Jung Yu ,  Tengzhou Ma ,  Seshadri Ganguli ,  Tuerxun Ailihumaer ,  Yogesh Sharma ,  Debaditya Chatterjee

IPC: C23C16/455 ,  C23C16/08 ,  C23C16/18

CPC classification number: C23C16/45553 ,  C23C16/08 ,  C23C16/18

Abstract: Methods for depositing metal films using a metal halide and metal organic precursors are described. The substrate is exposed to a first metal precursor and a second metal precursor to form the metal film. The exposures can be sequential or simultaneous. The metal films are relatively pure with a low carbon content.

公开(公告)号：US11639547B2

公开(公告)日：2023-05-02

申请号：US16401467

申请日：2019-05-02

Applicant: Applied Materials, Inc.

Inventor： Prerna Goradia ,  Jennifer Y. Sun ,  Xiaowei Wu ,  Geetika Bajaj ,  Atul Chaudhari ,  Ankur Kadam

IPC: C23C16/44 ,  C23C16/455 ,  H01J37/32 ,  C23C16/18 ,  C23C16/27 ,  C23C16/40

Abstract: Described herein are articles, systems and methods where a halogen resistant coating is deposited onto a surface of a chamber component using an atomic layer deposition (ALD) process. The halogen resistant coating has an optional amorphous seed layer and a transition metal-containing layer. The halogen resistant coating uniformly covers features of the chamber component, such as those having an aspect ratio of about 3:1 to about 300:1.

公开(公告)号：US20150147879A1

公开(公告)日：2015-05-28

申请号：US14483578

申请日：2014-09-11

Applicant: Applied Materials, Inc.

Inventor： Amit Chatterjee ,  Geetika Bajaj ,  Pramit Manna ,  He Ren ,  Tapash Chakraborty ,  Srinivas D. Nemani ,  Mehul Naik ,  Robert Jan visser ,  Abhijit Basu Mallick

IPC: H01L21/768

CPC classification number: H01L21/76834 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76838 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of depositing thin, low dielectric constant layers that are effective diffusion barriers on metal interconnects of semiconductor circuits are described. A self-assembled monolayer (SAM) of molecules each having a head moiety and a tail moiety are deposited on the metal. The SAM molecules self-align, wherein the head moiety is formulated to selectively bond to the metal layer leaving the tail moiety disposed at a distal end of the molecule. A dielectric layer is subsequently deposited on the SAM, chemically bonding to the tail moiety of the SAM molecules.

Abstract translation: 描述了在半导体电路的金属互连上沉积有效扩散阻挡层的薄的低介电常数层的方法。 每个具有头部和尾部的分子的自组装单层（SAM）沉积在金属上。 SAM分子自对准，其中头部部分被配制成选择性地键合到金属层，离开设置在分子远端的尾部。 随后在SAM上沉积介电层，化学键合到SAM分子的尾部。

公开(公告)号：US20240222195A1

公开(公告)日：2024-07-04

申请号：US18108719

申请日：2023-02-13

Applicant: Applied Materials, Inc.

Inventor： Tianyi Huang ,  Srinivas Gandikota ,  Yixiong Yang ,  Tengzhou Ma ,  Steven C.H. Hung ,  Hsin-Jung Yu ,  Geetika Bajaj

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/823462 ,  H01L29/42392 ,  H01L29/78696

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. Advantageously, the embodiments of the present disclosure provide methods of manufacturing electronic devices that achieve desired dipole effect without an annealing process. To achieve desired dipole effect that is “thinner” than 3 Å, embodiments of the disclosure advantageously include methods of controlling surface adsorption equilibrium and, in turn, controlling the fraction of substrate surface atomic sites that are occupied by dipole species, which is not considered to be achievable by ALD processes.

公开(公告)号：US12004337B2

公开(公告)日：2024-06-04

申请号：US17985065

申请日：2022-11-10

Applicant: Applied Materials, Inc.

Inventor： Gayatri Natu ,  Geetika Bajaj ,  Prerna Goradia ,  Darshan Thakare ,  David Fenwick ,  XiaoMing He ,  Sanni Seppaelae ,  Jennifer Sun ,  Rajkumar Thanu ,  Jeff Hudgens ,  Karuppasamy Muthukamatchy ,  Arun Dhayalan

IPC: H05K9/00 ,  H01J37/20 ,  H01J37/32 ,  H01L21/687 ,  H05F1/02

CPC classification number: H05K9/0064 ,  H01J37/20 ,  H01J37/32477 ,  H01J37/32495 ,  H01L21/68707 ,  H01L21/68757 ,  H05F1/02

Abstract: Disclosed in some embodiments is a chamber component (such as an end effector body) coated with an ultrathin electrically-dissipative material to provide a dissipative path from the coating to the ground. The coating may be deposited via a chemical precursor deposition to provide a uniform, conformal, and porosity free coating in a cost effective manner. In an embodiment wherein the chamber component comprises an end effector body, the end effector body may further comprise replaceable contact pads for supporting a substrate and the contact surface of the contact pads head may also be coated with an electrically-dissipative material.

公开(公告)号：US11976357B2

公开(公告)日：2024-05-07

申请号：US16698549

申请日：2019-11-27

Applicant: Applied Materials, Inc.

Inventor： Geetika Bajaj ,  Yogita Pareek ,  Prerna Sonthalia Goradia ,  Ankur Kadam

IPC: C23C16/455 ,  C23C16/02 ,  C23C16/40 ,  C23C16/44 ,  H01J37/32

CPC classification number: C23C16/45536 ,  C23C16/0272 ,  C23C16/40 ,  C23C16/4404 ,  C23C16/45553 ,  H01J37/32467 ,  H01J37/32495

Abstract: Embodiments of the disclosure provide methods for fabricating or otherwise forming a protective coating containing cerium oxide on processing chamber surfaces and/or components, such as surfaces which are exposed to a plasma within a processing chamber. In one or more embodiments, a method of forming a protective coating within a processing chamber includes depositing a cerium oxide layer on a chamber surface or a chamber component during an atomic layer deposition (ALD) process. The ALD process includes sequentially exposing the chamber surface or the chamber component to a cerium precursor, a purge gas, an oxidizing agent, and the purge gas during an ALD cycle, and repeating the ALD cycle to deposit the cerium oxide layer.

公开(公告)号：US20230420486A1

公开(公告)日：2023-12-28

申请号：US18208710

申请日：2023-06-12

Applicant: Applied Materials, Inc.

Inventor： Geetika Bajaj ,  Shonal Chouksey ,  Amit Kumar Roy ,  Darshan Thakare ,  Seshadri Ganguli ,  Gopi Chandran Ramachandran ,  Srinivas Gandikota ,  Jayeeta Sen

IPC: H01L21/02

CPC classification number: H01L28/40 ,  H01L21/02271

Abstract: Exemplary methods of semiconductor processing may include providing a first precursor to a semiconductor processing chamber. A substrate may be disposed within a processing region of the semiconductor processing chamber. The first precursor may include one or more of niobium, tantalum, or titanium. The methods may include contacting the substrate with the first precursor. The contacting may form a layer of metal on the substrate. The methods may include providing a second precursor to a semiconductor processing chamber. The second precursor comprises oxygen. The methods may include contacting the layer of metal with the second precursor. The contacting may form a layer of metal oxide on the substrate. The layer of metal oxide may be one or more of niobium oxide, tantalum oxide, or titanium oxide.

公开(公告)号：US10886137B2

公开(公告)日：2021-01-05

申请号：US16399391

申请日：2019-04-30

Applicant: Applied Materials, Inc.

Inventor： Prerna Sonthalia Goradia ,  Yogita Pareek ,  Geetika Bajaj ,  Robert Jan Visser ,  Nitin K. Ingle

IPC: H01L21/311 ,  H01L21/67

Abstract: Exemplary methods for selective etching of semiconductor materials may include flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber. The methods may also include flowing a silicon-containing suppressant into the processing region of the semiconductor processing chamber. The methods may further include contacting a substrate with the fluorine-containing precursor and the silicon-containing suppressant. The substrate may include an exposed region of silicon nitride and an exposed region of silicon oxide. The methods may also include selectively etching the exposed region of silicon nitride to the exposed region of silicon oxide.

公开(公告)号：US20190333776A1

公开(公告)日：2019-10-31

申请号：US16399391

申请日：2019-04-30

Applicant: Applied Materials, Inc.

Inventor： Prerna Sonthalia Goradia ,  Yogita Pareek ,  Geetika Bajaj ,  Robert Jan Visser ,  Nitin K. Ingle

IPC: H01L21/311 ,  H01L21/67

Abstract: Exemplary methods for selective etching of semiconductor materials may include flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber. The methods may also include flowing a silicon-containing suppressant into the processing region of the semiconductor processing chamber. The methods may further include contacting a substrate with the fluorine-containing precursor and the silicon-containing suppressant. The substrate may include an exposed region of silicon nitride and an exposed region of silicon oxide. The methods may also include selectively etching the exposed region of silicon nitride to the exposed region of silicon oxide.