公开(公告)号：US20240063064A1

公开(公告)日：2024-02-22

申请号：US17891923

申请日：2022-08-19

申请人： Applied Materials, Inc.

发明人： Srinivas Gandikota ,  Yixiong Yang ,  Tianyi Huang ,  Tengzhou Ma ,  Seshadri Ganguli

IPC分类号： H01L21/8238 ,  H01L29/51 ,  H01L21/768 ,  H01L21/324

CPC分类号： H01L21/823821 ,  H01L29/517 ,  H01L21/76829 ,  H01L21/324 ,  H01L21/0228

摘要： Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise a dipole region and meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-κ dielectric layer on the interfacial layer, a dipole layer on the high-κ dielectric layer, and optionally, a capping layer on the dipole layer. In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-κ dielectric layer.

公开(公告)号：US20240222195A1

公开(公告)日：2024-07-04

申请号：US18108719

申请日：2023-02-13

申请人： Applied Materials, Inc.

发明人： Tianyi Huang ,  Srinivas Gandikota ,  Yixiong Yang ,  Tengzhou Ma ,  Steven C.H. Hung ,  Hsin-Jung Yu ,  Geetika Bajaj

IPC分类号： H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L21/823462 ,  H01L29/42392 ,  H01L29/78696

摘要： Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. Advantageously, the embodiments of the present disclosure provide methods of manufacturing electronic devices that achieve desired dipole effect without an annealing process. To achieve desired dipole effect that is “thinner” than 3 Å, embodiments of the disclosure advantageously include methods of controlling surface adsorption equilibrium and, in turn, controlling the fraction of substrate surface atomic sites that are occupied by dipole species, which is not considered to be achievable by ALD processes.

公开(公告)号：US20240360557A1

公开(公告)日：2024-10-31

申请号：US18139121

申请日：2023-04-25

申请人： Applied Materials, Inc.

发明人： Srinivas Gandikota ,  Yixiong Yang ,  Tianyi Huang ,  Geetika Bajaj ,  Hsin-Jung Yu ,  Tengzhou Ma ,  Seshadri Ganguli ,  Tuerxun Ailihumaer ,  Yogesh Sharma ,  Debaditya Chatterjee

IPC分类号： C23C16/455 ,  C23C16/08 ,  C23C16/18

CPC分类号： C23C16/45553 ,  C23C16/08 ,  C23C16/18

摘要： Methods for depositing metal films using a metal halide and metal organic precursors are described. The substrate is exposed to a first metal precursor and a second metal precursor to form the metal film. The exposures can be sequential or simultaneous. The metal films are relatively pure with a low carbon content.

公开(公告)号：US20240363723A1

公开(公告)日：2024-10-31

申请号：US18140850

申请日：2023-04-28

申请人： Applied Materials, Inc.

发明人： Srinivas Gandikota ,  Tengzhou Ma ,  Geetika Bajaj ,  Debaditya Chatterjee ,  Hsin-Jung Yu ,  Pei Hsuan Lin ,  Yixiong Yang

IPC分类号： H01L29/51 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40

CPC分类号： H01L29/513 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/401 ,  H01L29/517

摘要： Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. The method comprises forming a P-dipole stack and an N-dipole stack on a semiconductor substrate by: depositing an interfacial layer (e.g., silicon oxide (SiOx)) on the top surface of the channel; depositing a hafnium-containing layer comprising hafnium oxide (HfOx) and having a thickness of less than or equal to 5 Å on the interfacial layer; and depositing a dipole layer comprising lanthanum nitride (LaN) on the hafnium-containing layer.

公开(公告)号：US20240266414A1

公开(公告)日：2024-08-08

申请号：US18124674

申请日：2023-03-22

申请人： Applied Materials, Inc.

发明人： Srinivas Gandikota ,  Yixiong Yang ,  Tengzhou Ma ,  Tianyi Huang ,  Geetika Bajaj ,  Hsin-Jung Yu ,  Seshadri Ganguli

IPC分类号： H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： Embodiments of the disclosure advantageously provide methods of manufacturing semiconductor devices having multi-Vt capability in the scaled space between nanosheets in advanced GAA nodes. One or more embodiments provide an integration scheme to advantageously reduce the gate resistance by combining n-/p-dipole and mid-gap metal with low resistance to achieve desired work function and low-resistance metal gate. In one or more embodiments, a mid-gap metal is used to fill nanosheets and act as a liner for subsequent fill by a low resistance metal. After dipole engineering, instead of filling the gate-all-around nanosheet with traditional n or p metal, in one or more embodiments, the nanosheet is advantageously filled with a single work function mid-gap metal to achieve n and p work function. If the work function was shifted in either P-dipole or N-dipole bandedge after dipole engineering, the mid-gap materials can also shift the bandedge the opposite way.

公开(公告)号：US20240204061A1

公开(公告)日：2024-06-20

申请号：US18067979

申请日：2022-12-19

申请人： Applied Materials, Inc.

发明人： Srinivas Gandikota ,  Yixiong Yang ,  Yongjing Lin ,  Tuerxun Ailihumaer ,  Tengzhou Ma ,  Yuanhua Zheng ,  Zhihui Liu ,  Shih Chung Chen ,  Janardhan Devrajan ,  Yi Xu ,  Yu Lei ,  Mandyam Sriram

IPC分类号： H01L29/40 ,  H01L29/423

CPC分类号： H01L29/401 ,  H01L29/42392 ,  H01L29/4925

摘要： Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide methods to reduce the resistance of the work function layer of an electronic device, as well as using a low resistivity metal for filling the gate.

公开(公告)号：US20230377879A1

公开(公告)日：2023-11-23

申请号：US17747978

申请日：2022-05-18

申请人： Applied Materials, Inc.

发明人： Srinivas Gandikota ,  Elizabeth Mao ,  Tianyi Huang ,  Tengzhou Ma ,  Chi-Chou Lin ,  Yixiong Yang

IPC分类号： H01L21/02

CPC分类号： H01L21/02362 ,  H01L21/02153 ,  H01L21/02181

摘要： Embodiments of the present disclosure are related to methods of preventing aluminum diffusion in a metal gate stack (e.g., high-κ metal gate (HKMG) stacks and nMOS FET metal gate stacks). Some embodiments relate to a barrier layer for preventing aluminum diffusion into high-κ metal oxide layers. The barrier layer described herein is configured to reduce threshold voltage (Vt) shift and reduce leakage in the metal gate stacks. Additional embodiments relate to methods of forming a metal gate stack having the barrier layer described herein. The barrier layer may include one or more of amorphous silicon (a-Si), titanium silicon nitride (TiSiN), tantalum nitride (TaN), or titanium tantalum nitride (TiTaN).