Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. The method comprises forming a P-dipole stack and an N-dipole stack on a semiconductor substrate by: depositing an interfacial layer (e.g., silicon oxide (SiOx)) on the top surface of the channel; depositing a hafnium-containing layer comprising hafnium oxide (HfOx) and having a thickness of less than or equal to 5 Å on the interfacial layer; and depositing a dipole layer comprising lanthanum nitride (LaN) on the hafnium-containing layer.