公开(公告)号：US20090104779A1

公开(公告)日：2009-04-23

申请号：US12289002

申请日：2008-10-17

申请人： Akiyoshi Seko ,  Natsuki Sato ,  Isamu Asano

发明人： Akiyoshi Seko ,  Natsuki Sato ,  Isamu Asano

IPC分类号： H01L21/308 ,  H01L45/00

CPC分类号： H01L45/1233 ,  G11C13/0004 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1273 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/148 ,  H01L45/16

摘要： An area where a lower electrode is in contact with a variable resistance material needs to be reduced to lower the power consumption of a variable resistance memory device. The present invention is to provide a method of producing a variable resistance memory element whereby the lower electrode can be formed smaller. Combining an anisotropic etching process with an isotropic etching process enables the lower electrode to be formed smaller.

摘要翻译： 需要减小下电极与可变电阻材料接触的区域，以降低可变电阻存储器件的功耗。 本发明提供一种制造可变电阻存储元件的方法，由此可以使下电极形成得更小。 将各向异性蚀刻工艺与各向同性蚀刻工艺相结合，能够使下部电极形成得更小。

公开(公告)号：US08129709B2

公开(公告)日：2012-03-06

申请号：US12618302

申请日：2009-11-13

申请人： Akiyoshi Seko ,  Yukio Fuji ,  Natsuki Sato ,  Isamu Asano

发明人： Akiyoshi Seko ,  Yukio Fuji ,  Natsuki Sato ,  Isamu Asano

IPC分类号： H01L45/00

CPC分类号： H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： A nonvolatile memory device (21) is provided with a semiconductor substrate, a plurality of active regions (3) formed on the semiconductor substrate and extending in a band, a plurality of select active elements (23) formed in the active regions (3) and having a first impurity diffusion region and a second impurity diffusion region, a plurality of first electrodes (13) electrically connected to the first impurity diffusion region, a variable resistance layer (12) electrically connected to the first electrodes (13), and a plurality of second electrodes electrically connected to the variable resistance layer (12). Among the plurality of first electrodes (13) and the plurality of second electrodes, an array direction of at least one pair of the first electrodes (13) and the second electrodes that are electrically connected to the same variable resistance layer (12), and a direction of extension of the activation regions (3) are not parallel.

摘要翻译： 非易失性存储器件（21）设置有半导体衬底，形成在半导体衬底上并在带中延伸的多个有源区（3），形成在有源区（3）中的多个选择有源元件（23） 并具有第一杂质扩散区域和第二杂质扩散区域，与第一杂质扩散区域电连接的多个第一电极（13），与第一电极（13）电连接的可变电阻层（12），以及 电连接到可变电阻层（12）的多个第二电极。 在多个第一电极（13）和多个第二电极中，电连接到同一可变电阻层（12）的至少一对第一电极（13）和第二电极的排列方向，以及 激活区域（3）的延伸方向不平行。

公开(公告)号：US20100078616A1

公开(公告)日：2010-04-01

申请号：US12569489

申请日：2009-09-29

申请人： Akiyoshi Seko ,  Natsuki Sato ,  Isamu Asano

发明人： Akiyoshi Seko ,  Natsuki Sato ,  Isamu Asano

IPC分类号： H01L47/00 ,  H01L21/20

CPC分类号： H01L45/04 ,  H01L45/145

摘要： A nonvolatile memory device has a first insulating layer, a variable resistance layer provided on the first insulating layer and having a variable resistance material, and a first electrode and second electrode electrically connected with the variable resistance layer. The variable resistance layer has a variable resistance region as a data storing region and a thickness-changing region continuously extending from the variable resistance region and gradually becoming thicker from the variable resistance region.

摘要翻译： 非易失性存储器件具有第一绝缘层，设置在第一绝缘层上并具有可变电阻材料的可变电阻层，以及与可变电阻层电连接的第一电极和第二电极。 可变电阻层具有作为数据存储区域的可变电阻区域和从可变电阻区域连续延伸并从可变电阻区域逐渐变厚的厚度变化区域。

公开(公告)号：US08510613B2

公开(公告)日：2013-08-13

申请号：US12929939

申请日：2011-02-25

申请人： Akiyoshi Seko

发明人： Akiyoshi Seko

IPC分类号： G11C29/00

CPC分类号： G11C13/0004 ,  G11C13/0023 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069

摘要： A method includes temporarily storing write-data to be written into non-volatile memory cells, respectively, the memory cells being divided into cell groups, performing a first operation including write-phases performed in series and on an associated cell group and including applying a write-voltage to the memory cells belonging to the associated cell group in response to an associated write-data to be written into the memory cells belonging to the cell groups, and performing a second operation after the first operation is completed, which includes read-phases performed in series and on an associated cell group and including applying a first read-voltage to the memory cell or cells belonging to the associated one of the cell groups to produce first read-data therefrom, and comparing the first read-data with the write-data to be written into the memory cells belonging to the associated cell groups to produce comparison data.

摘要翻译： 一种方法包括将要被写入非易失性存储单元的写入数据临时存储在存储器单元中，该存储器单元被分成单元组，执行包括串联执行的写入阶段和相关单元组的第一操作，并且包括应用 响应于要写入属于所述单元组的存储单元的关联写入数据，将属于所述关联单元组的存储单元写入电压，并且在所述第一操作完成之后执行第二操作， 并且包括将属于所述相关一个所​​述单元组的所述存储单元或单元施加第一读取电压以从其产生第一读取数据，以及将所述第一读取数据与所述第一读取数据进行比较 将写入数据写入属于相关联的单元组的存储单元以产生比较数据。

公开(公告)号：US07985693B2

公开(公告)日：2011-07-26

申请号：US12289002

申请日：2008-10-17

申请人： Akiyoshi Seko ,  Natsuki Sato ,  Isamu Asano

发明人： Akiyoshi Seko ,  Natsuki Sato ,  Isamu Asano

IPC分类号： H01L21/302

CPC分类号： H01L45/1233 ,  G11C13/0004 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1273 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/148 ,  H01L45/16

摘要： An area where a lower electrode is in contact with a variable resistance material needs to be reduced to lower the power consumption of a variable resistance memory device. The present invention is to provide a method of producing a variable resistance memory element whereby the lower electrode can be formed smaller. Combining an anisotropic etching process with an isotropic etching process enables the lower electrode to be formed smaller.

摘要翻译： 需要减小下电极与可变电阻材料接触的区域，以降低可变电阻存储器件的功耗。 本发明提供一种制造可变电阻存储元件的方法，由此可以使下电极形成得更小。 将各向异性蚀刻工艺与各向同性蚀刻工艺相结合，能够使下部电极形成得更小。

公开(公告)号：US20090101885A1

公开(公告)日：2009-04-23

申请号：US12285686

申请日：2008-10-10

申请人： Akiyoshi Seko ,  Natsuki Sato ,  Isamu Asano

发明人： Akiyoshi Seko ,  Natsuki Sato ,  Isamu Asano

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L27/2436 ,  G11C13/0004 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/148 ,  H01L45/16

摘要： An area where a lower electrode is in contact with a variable resistance material needs to be reduced in order to lower the power consumption of a variable resistance memory device. The present invention provides a method of producing a variable resistance memory element whereby the lower electrode can be more finely formed. The method of producing a semiconductor device according to the present invention includes forming a small opening by utilizing cubical expansion due to the oxidation of silicon. Thereby forming the lower electrode smaller than that can be formed by lithography techniques.

摘要翻译： 需要减小下电极与可变电阻材料接触的区域，以降低可变电阻存储器件的功耗。 本发明提供一种制造可变电阻存储元件的方法，由此可以更细地形成下电极。 根据本发明的半导体器件的制造方法包括通过利用硅的氧化的立方膨胀来形成小开口。 从而形成小于此的下电极可以通过光刻技术形成。

公开(公告)号：US09589608B2

公开(公告)日：2017-03-07

申请号：US12730859

申请日：2010-03-24

申请人： Akiyoshi Seko

发明人： Akiyoshi Seko

IPC分类号： G11C7/02 ,  G11C7/12 ,  G11C7/18 ,  G11C13/00

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/18 ,  G11C13/0026 ,  G11C13/004

摘要： In a semiconductor memory device storing a resistance difference as information, a long time is taken so as to charge and/or discharge a selected cell by an equalizer circuit, which results in a difficulty of a high speed operation. A selection circuit puts, in a selected state, at least three bit lines which includes a selected bit line connected to a selected memory cell together with unselected bit lines adjacent to the selected bit line on both sides of the selected bit line. The selected and the unselected bit lines are coupled to sense amplifiers through an equalizer circuit. The equalizer circuit puts both the selected and the unselected bit lines into charging states and thereafter puts only the selected bit line into a discharging state to perform a sensing operation. On the other hand, the unselected bit lines are continuously kept at the charging states during the sensing operation. This makes it possible to perform the sensing operation at a high speed with a rare malfunction.

摘要翻译： 在存储电阻差作为信息的半导体存储器件中，采取长时间以便通过均衡器电路对所选择的单元进行充电和/或放电，这导致高速操作的困难。 选择电路以选定的状态放置至少三条位线，其包括连接到所选择的存储器单元的选定位线以及与选定位线两侧所选位线相邻的未选定位线。 所选择的和未选择的位线通过均衡器电路耦合到读出放大器。 均衡器电路将所选择的和未选择的位线都放入充电状态，然后仅将所选位线置于放电状态以执行感测操作。 另一方面，在感测操作期间，未选择的位线被连续地保持在充电状态。 这使得可以以罕见的故障高速执行感测操作。

公开(公告)号：US07780001B2

公开(公告)日：2010-08-24

申请号：US11192463

申请日：2005-07-26

申请人： Akiyoshi Seko

发明人： Akiyoshi Seko

IPC分类号： B65D85/57

CPC分类号： G11B33/0422 ,  G11B33/0494

摘要： A file wrapper for wrapping is provided. The file wrapper for wrapping comprises a file wrapper for wrapping comprising: a the cutting body, which comprises a unit piece of a covering paper and a backing paper of integral constitution that is bent to form a bag shape, sealing pieces provided to the covering paper and the backing paper, at the opening portion of the bag shape for inserting commodities, respectively, and side sticking pieces provided to the both sides portion of the covering paper. The one sealing piece is provided with a stopper of commodities after inserting them, and the other sealing piece is provided with the connecting piece inserted in the notch hole of the stopper and engaged thereto.

摘要翻译： 提供了一个用于包装的文件包装。 用于包装的文件包装件包括用于包装的文件包装件，包括：切割体，其包括被覆的纸的单位片和被弯曲形成袋形状的整体构造的背纸，设置在覆盖纸上的密封片 以及背纸，分别在用于插入商品的袋形的开口部分和设置在覆盖纸的两侧部分的侧贴片。 一个密封件在插入之后设置有商品塞子，另一个密封件设置有插入塞子的切口孔中并与其接合的连接片。

公开(公告)号：US20100195415A1

公开(公告)日：2010-08-05

申请号：US12656484

申请日：2010-02-01

申请人： Akiyoshi Seko

发明人： Akiyoshi Seko

IPC分类号： G11C5/14 ,  G11C7/02 ,  G11C7/00

CPC分类号： G11C7/02 ,  G11C5/145 ,  G11C5/147 ,  G11C7/12 ,  G11C11/1673 ,  G11C11/1693

摘要： A memory device is configured such that, in a read access: a first switch and a second switch are turned on in a pre-charge period before a memory cell is accessed so that charges of a bit line charge voltage generating circuit are distributed to a bit line and a reference bit line, to thereby charge the bit line and the reference bit line to an initial voltage. After the charge, a selected memory cell is connected to the bit line, the reference bit line is connected to a reference voltage generating circuit, and a voltage differential type sense amplifier amplifies a difference voltage between a voltage of the bit line decreased by discharge of the selected memory cell and a voltage of the reference bit line generated by the reference voltage generating circuit, to thereby read out memory cell data.

摘要翻译： 存储器件被配置为使得在读取访问中：第一开关和第二开关在存储单元被访问之前的预充电周期中被接通，使得位线充电电压产生电路的电荷被分配到 位线和参考位线，从而将位线和参考位线充电到初始电压。 在充电之后，选择的存储单元连接到位线，参考位线连接到参考电压产生电路，并且电压差分型读出放大器放大位线减小的电压之间的差值电压 所选择的存储单元和由参考电压产生电路产生的参考位线的电压，从而读出存储单元数据。

公开(公告)号：US08787068B2

公开(公告)日：2014-07-22

申请号：US13440633

申请日：2012-04-05

申请人： Akiyoshi Seko ,  Tatsuya Matano

发明人： Akiyoshi Seko ,  Tatsuya Matano

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0038 ,  G11C2013/0071 ,  G11C2213/74 ,  G11C2213/79

摘要： A semiconductor device includes first and second interconnects, a variable resistance element that may assume a first resistance value or a second resistance value in response to the current flowing therein, first and second transistors connected between the first and second interconnects in series with each other on both sides of the variable resistance element, and a power supply circuit unit that delivers the power supply to a control electrode of the first transistor. The power supply circuit unit supplies the power of a first power supply when the variable resistance element is to make transition to the first resistance value and the power supply circuit unit supplies the power of a second power supply when the variable resistance element is to make transition to the second resistance value, thereby allowing transitioning of the resistance values of the variable resistance element.

摘要翻译： 半导体器件包括第一和第二互连，可变电阻元件，其响应于其中流过的电流而呈现第一电阻值或第二电阻值，第一和第二晶体管彼此串联连接在第一和第二互连之间 可变电阻元件的两侧，以及将电源输送到第一晶体管的控制电极的电源电路单元。 当可变电阻元件要转变到第一电阻值时，电源电路单元提供第一电源的电力，并且当可变电阻元件要转变时，电源电路单元提供第二电源的电力 到第二电阻值，从而允许可变电阻元件的电阻值的转变。