公开(公告)号：US20130084651A1

公开(公告)日：2013-04-04

申请号：US13639582

申请日：2011-04-04

申请人： Ryo Kojima ,  Kenta Noda ,  Yoshiro Sato ,  Natsuki Sato ,  Kaduho Ashizawa

发明人： Ryo Kojima ,  Kenta Noda ,  Yoshiro Sato ,  Natsuki Sato ,  Kaduho Ashizawa

IPC分类号： G01N33/53

摘要： Disclosed is a test instrument for measuring an analyte in a liquid sample by a noble metal colloid aggregation measurement method. The test instrument involves a reaction chamber in which at least the liquid sample is to be reacted with a reagent, wherein the reagent is adhered on at least a part of a surface constituting the reaction chamber in a dried state, and the reagent enables the measurement of the analyte by a noble metal colloid aggregation measurement method. The test instrument additionally involves a supply section for supplying the liquid sample and a flow path for delivering the liquid sample that has been supplied to the supply section to the reaction chamber, wherein the liquid sample that has been supplied to the supply section is delivered to the reaction chamber through the flow path to cause the liquid sample to be brought into contact with the reagent that has been adhered in a dried state, thereby producing a difference in pressure between the supply section and the reaction chamber for the purpose of dispersing the reagent in the liquid sample. When the test instrument is used, the measurement based on an absorbance at a visible region can be achieved, the analyte can be measured accurately within a short time, and the measurement suitable for a POCT field can be achieved.

摘要翻译： 公开了一种用于通过贵金属胶体聚集测量方法测量液体样品中的分析物的测试仪器。 测试仪器包括反应室，其中至少液体样品将与试剂反应，其中试剂在干燥状态下粘附在构成反应室的表面的至少一部分上，并且该试剂能够进行测量 的分析物通过贵金属胶体聚集测量方法。 测试仪器还包括用于供应液体样品的供应部分和用于将已经供应到供应部分的液体样品输送到反应室的流路，其中已经供应到供应部分的液体样品被递送到 反应室通过流路使液体样品与干燥状态下已经粘附的试剂接触，从而产生供给部和反应室之间的压力差，以分散试剂 在液体样品中。 当使用测试仪器时，可以实现基于可见光区域的吸光度的测量，可以在短时间内精确测量分析物，并且可以实现适合于POCT场的测量。

公开(公告)号：US08296972B2

公开(公告)日：2012-10-30

申请号：US12414141

申请日：2009-03-30

申请人： Natsuki Sato ,  Tetsuo Yamamoto ,  Yoshinobu Watanabe ,  Satoshi Kishimoto

发明人： Natsuki Sato ,  Tetsuo Yamamoto ,  Yoshinobu Watanabe ,  Satoshi Kishimoto

IPC分类号： A43B23/00

CPC分类号： A43B23/047 ,  A43B1/04 ,  A43B9/12

摘要： A shoe 1 of the present invention includes an upper 2 made of a stretchable fabric. The stretchable fabric is integrated with a sole 3 in a state of being stretched. Further, a method of manufacturing the shoe 1 of the present invention is a method of manufacturing a shoe using a stretchable fabric for the upper 2. The method includes steps of: producing an upper pattern using a last having a size smaller than that of the sole 3 as a base; producing the upper 2 with the stretchable fabric being stretched by stretching the upper pattern and fitting the upper pattern onto a last having a size that matches the sole 3; and integrating the upper 2 with the stretchable fabric being stretched with the sole 3.

摘要翻译： 本发明的鞋1包括由可伸缩织物制成的鞋面2。 伸缩性织物与被拉伸状态的鞋底3一体化。 此外，制造本发明的鞋1的方法是使用上部2的伸缩性织物制造鞋子的方法。该方法包括以下步骤：使用具有小于 鞋底3为基地; 通过拉伸上部图案并将上部图案装配到具有与鞋底3相匹配的尺寸的最后部分上，使可伸展织物拉伸; 并且将上部2与被鞋底3拉伸的可伸展织物整合。

公开(公告)号：US08129709B2

公开(公告)日：2012-03-06

申请号：US12618302

申请日：2009-11-13

申请人： Akiyoshi Seko ,  Yukio Fuji ,  Natsuki Sato ,  Isamu Asano

发明人： Akiyoshi Seko ,  Yukio Fuji ,  Natsuki Sato ,  Isamu Asano

IPC分类号： H01L45/00

CPC分类号： H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： A nonvolatile memory device (21) is provided with a semiconductor substrate, a plurality of active regions (3) formed on the semiconductor substrate and extending in a band, a plurality of select active elements (23) formed in the active regions (3) and having a first impurity diffusion region and a second impurity diffusion region, a plurality of first electrodes (13) electrically connected to the first impurity diffusion region, a variable resistance layer (12) electrically connected to the first electrodes (13), and a plurality of second electrodes electrically connected to the variable resistance layer (12). Among the plurality of first electrodes (13) and the plurality of second electrodes, an array direction of at least one pair of the first electrodes (13) and the second electrodes that are electrically connected to the same variable resistance layer (12), and a direction of extension of the activation regions (3) are not parallel.

摘要翻译： 非易失性存储器件（21）设置有半导体衬底，形成在半导体衬底上并在带中延伸的多个有源区（3），形成在有源区（3）中的多个选择有源元件（23） 并具有第一杂质扩散区域和第二杂质扩散区域，与第一杂质扩散区域电连接的多个第一电极（13），与第一电极（13）电连接的可变电阻层（12），以及 电连接到可变电阻层（12）的多个第二电极。 在多个第一电极（13）和多个第二电极中，电连接到同一可变电阻层（12）的至少一对第一电极（13）和第二电极的排列方向，以及 激活区域（3）的延伸方向不平行。

公开(公告)号：US07829878B2

公开(公告)日：2010-11-09

申请号：US11845120

申请日：2007-08-27

申请人： Natsuki Sato

发明人： Natsuki Sato

IPC分类号： H01L47/00

CPC分类号： H01L45/1233 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/143 ,  H01L45/148 ,  H01L45/16

摘要： A semiconductor device includes an interlayer insulating film formed on a semiconductor substrate to cover a lower electrode, a side-wall insulating film formed on a side wall of a contact hole formed through the interlayer insulating film to a depth reaching the lower electrode, a heater formed in the interior of the contact hole defined by the side-wall insulating film, and a phase-change film in contact with the top surface of the heater. The heater is in contact with the lower electrode at the bottom surface within the contact hole, and the top surface thereof is located at a lower level than that of the top surface of the side-wall insulating film. The top surface of the heater is located at a lower level than the top surface of the side-wall insulating film by an extent equal to or greater than a thickness of the phase-change film.

摘要翻译： 半导体器件包括形成在半导体衬底上以覆盖下电极的层间绝缘膜，形成在通过层间绝缘膜形成的接触孔的侧壁上的侧壁绝缘膜，到达下电极的深度，加热器 形成在由侧壁绝缘膜限定的接触孔的内部，以及与加热器的顶表面接触的相变膜。 加热器与接触孔底面的下电极接触，其顶面位于比侧壁绝缘膜的上表面低的位置。 加热器的上表面位于与侧壁绝缘膜的顶表面相比等于或大于相变膜厚度的程度的较低水平处。

公开(公告)号：US20100078616A1

公开(公告)日：2010-04-01

申请号：US12569489

申请日：2009-09-29

申请人： Akiyoshi Seko ,  Natsuki Sato ,  Isamu Asano

发明人： Akiyoshi Seko ,  Natsuki Sato ,  Isamu Asano

IPC分类号： H01L47/00 ,  H01L21/20

CPC分类号： H01L45/04 ,  H01L45/145

摘要： A nonvolatile memory device has a first insulating layer, a variable resistance layer provided on the first insulating layer and having a variable resistance material, and a first electrode and second electrode electrically connected with the variable resistance layer. The variable resistance layer has a variable resistance region as a data storing region and a thickness-changing region continuously extending from the variable resistance region and gradually becoming thicker from the variable resistance region.

摘要翻译： 非易失性存储器件具有第一绝缘层，设置在第一绝缘层上并具有可变电阻材料的可变电阻层，以及与可变电阻层电连接的第一电极和第二电极。 可变电阻层具有作为数据存储区域的可变电阻区域和从可变电阻区域连续延伸并从可变电阻区域逐渐变厚的厚度变化区域。

公开(公告)号：US20080120871A1

公开(公告)日：2008-05-29

申请号：US11982218

申请日：2007-10-31

申请人： Natsuki Sato ,  Tetsuo Yamamoto

发明人： Natsuki Sato ,  Tetsuo Yamamoto

IPC分类号： A43B7/14 ,  A43B5/00 ,  A43B21/00 ,  A43B23/00 ,  A43B23/08

CPC分类号： A43B13/181 ,  A43B23/0235 ,  A43B23/0275 ,  A43B23/047 ,  A43C1/00

摘要： An upper structure for a shoe that improves a fit of the heel portion during heel contact with the ground to the push off motion of a foot. The upper structure includes an upper body 30, and an outside upper member 31 that overlaps the lateral side of the upper body 30 to cover the talus T of the foot and whose bottom side edge portion 31a is fixedly attached to the bottom surface of the upper body 30. The rear end portion A of the bottom side edge portion 31a of the outside upper member 31 is located at the rear of the load centerline C of the calcaneus and the rear side edge portion 31c of the outside upper member 31 is provided separately from the upper body 30 at the rear of the talus T of the foot. The instep side edge portion 31b of the outside upper member 31 is connected to the shoelace 4. On the lateral side of the heel portion of the upper body 30 is provided a region 10 that is expandable and contractible in the longitudinal direction. The top end of the region 10 extends to the opening of the upper body 30 and the bottom end B of the region 10 is disposed in front of the load centerline C of the calcaneus and below the height h that corresponds to 55% of the lateral ankle height H of the foot.

摘要翻译： 一种用于鞋的上部结构，其改善了跟脚部接触地面期间脚后跟部分与脚的推开运动的配合。 上部结构包括上部主体30和与上部主体30的横向侧重叠以覆盖脚部的距离T并且其底部侧边缘部分31a固定地附接到底部表面的外部上部构件31 上身30。 外侧上部构件31的下侧边缘部31a的后端部A位于跟骨的负载中心线C的后方，并且外侧上部构件31的后侧缘部31c与 脚部的距离T的后方的上身30。 外侧上部构件31的脚背侧边缘部31b与鞋带4连接。 在上主体30的跟部的侧面设置有沿纵向可扩张和收缩的区域10。 区域10的顶端延伸到上主体30的开口，并且区域10的底端B设置在跟骨的负载中心线C的前方，并且低于对应于侧面的55％的高度h 脚踝高度H。

公开(公告)号：US5736775A

公开(公告)日：1998-04-07

申请号：US585993

申请日：1996-01-11

申请人： Natsuki Sato

发明人： Natsuki Sato

IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A semiconductor device includes a field insulating film, a channel stopper, and a diffusion layer. The field insulating film is formed on one major surface of a semiconductor substrate of a first conductivity type to surround an element region. The channel stopper of the first conductivity type is formed immediately below the field insulating film. The diffusion layer of an opposite conductivity type is formed to be adjacent to the channel stopper. The impurity concentration peak position of the diffusion layer substantially coincides with that of the channel stopper.

摘要翻译： 半导体器件包括场绝缘膜，沟道阻挡层和扩散层。 场绝缘膜形成在第一导电类型的半导体衬底的一个主表面上以围绕元件区域。 第一导电类型的沟道阻挡件形成在场绝缘膜的正下方。 相反导电型的扩散层形成为与通道阻挡件相邻。 扩散层的杂质浓度峰值位置与沟道阻挡层的杂质浓度峰值位置基本一致。

公开(公告)号：US5521111A

公开(公告)日：1996-05-28

申请号：US239403

申请日：1994-05-06

申请人： Natsuki Sato

发明人： Natsuki Sato

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10861 ,  H01L27/10835 ,  H01L28/40

摘要： A memory cell is implemented by a series combination of a field effect transistor and a trench-stacked type storage capacitor, and an accumulating electrode is held in contact with a source region of the field effect transistor through an extremely narrow gap between a side spacer on a gate electrode of the field effect transistor and an isolation layer extending along a primary trench nested with the source region, wherein the side spacer is formed from a deposited doped polysilicon film and the isolation layer is formed by thermally oxidizing a wall portion of the primary trench so that the extremely narrow gap is defined without lithographic techniques.

摘要翻译： 存储单元通过场效应晶体管和沟槽层叠型存储电容器的串联组合来实现，并且累积电极通过侧面间隔物之间​​的极窄间隙与场效应晶体管的源极区域保持接触 场效应晶体管的栅电极和沿着源区域嵌套的主沟槽延伸的隔离层，其中侧隔离物由沉积的掺杂多晶硅膜形成，隔离层通过热氧化主层的壁部分而形成 沟槽，使得在没有光刻技术的情况下限定极窄的间隙。

公开(公告)号：US5424247A

公开(公告)日：1995-06-13

申请号：US924497

申请日：1992-08-04

申请人： Natsuki Sato

发明人： Natsuki Sato

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78 ,  H01L21/44

CPC分类号： H01L21/76814 ,  H01L21/76804 ,  H01L21/76831 ,  H01L2924/0002

摘要： In a method for making contact holes in a semiconductor device according to the invention, a first insulating film is deposited on a semiconductor chip, a plurality of contact holes are formed by sequentially performing isotropic etching and anisotropic etching, a second insulating film is deposited after the portions of the first insulating film constituting peripheries of the contact holes are subjected to a reflow process, and residue sidewall insulators are formed for the contact holes by keeping portions of the second insulating film only at sidewall portions of the contact holes when the second Insulating film is etched-back by an anisotropic etching process. The structure thus obtained enables to provide the contact holes whose peripheral edges are gently tapered thereby improving the step coverage of the Interconnect wiring material at the contact hole portions. This enables to avoid a possibility for the interconnect wiring layer to be broken, which may otherwise be caused by a poor step coverage of the interconnect wiring layer. The method enhances the production yield in the fabrication of the device and also enhances the reliability of the product.

摘要翻译： 在根据本发明的半导体器件中制造接触孔的方法中，第一绝缘膜沉积在半导体芯片上，通过依次执行各向同性蚀刻和各向异性蚀刻形成多个接触孔，第二绝缘膜沉积在 构成接触孔周边的第一绝缘膜的部分被进行回流处理，并且当第二绝缘体仅在接触孔的侧壁部分保持第二绝缘膜的一部分时，形成用于接触孔的残余侧壁绝缘体 通过各向异性蚀刻工艺对膜进行回蚀。 由此得到的结构能够提供周缘缓慢变细的接触孔，从而改善了接触孔部分处的互连布线材料的台阶覆盖。 这使得能够避免互连布线层破裂的可能性，否则可能由互连布线层的差的覆盖层引起。 该方法提高了器件制造中的生产成本，并提高了产品的可靠性。

公开(公告)号：US08215031B2

公开(公告)日：2012-07-10

申请号：US12380462

申请日：2009-02-27

申请人： Takaya Kimura ,  Koji Ito ,  Natsuki Sato

发明人： Takaya Kimura ,  Koji Ito ,  Natsuki Sato

IPC分类号： A43B13/18 ,  A43B13/20 ,  A43B21/24

CPC分类号： A43B13/181

摘要： A sole structure 1 for a shoe comprises an upper sheet portion 2 disposed on the upper side of the sole structure, and a plurality of curved sheet portions 3 (31-35) that are provided on the lower surface of the upper sheet portion 2, that have downwardly convexedly curved portions 31-35, respectively, and that are disposed side by side and partially overlapped with each other in the longitudinal direction. Each of the curved sheet portions 31-35 has a first end A (A1-A5) and a second end B (B1-B5) on the opposite sides of each of the downwardly convexedly curved portions 31-35. The first end A of the curved sheet portion 3 is located on the front side of the sole structure 1 and fixed to the lower surface of the upper sheet portion 2. The second end B of the curved sheet portion 3 is located on the rear side of the sole structure 1 and fixed to the external surface of the adjacent curved sheet portion 3.

摘要翻译： 用于鞋的鞋底结构1包括设置在鞋底结构的上侧的上片部分2和设置在上片部分2的下表面上的多个弯曲片部分3（31-35） 它们分别具有向下凸出的弯曲部分31-35，它们在纵向上并排设置并且彼此部分重叠。 每个弯曲片部分31-35在每个向下凸出的弯曲部分31-35的相对侧上具有第一端A（A1-A5）和第二端B（B1-B5）。 弯曲片部分3的第一端A位于鞋底结构1的前侧并固定到上片部2的下表面。弯曲片部分3的第二端B位于后侧 并且固定到相邻的弯曲片部3的外表面。