公开(公告)号：US08921977B2

公开(公告)日：2014-12-30

申请号：US13333564

申请日：2011-12-21

Applicant: Jen Jui Huang ,  Che Chi Lee ,  Shih Shu Tsai ,  Cheng Shun Chen ,  Shao Ta Hsu ,  Chao Wen Lay ,  Chun I Hsieh ,  Ching Kai Lin

Inventor： Jen Jui Huang ,  Che Chi Lee ,  Shih Shu Tsai ,  Cheng Shun Chen ,  Shao Ta Hsu ,  Chao Wen Lay ,  Chun I Hsieh ,  Ching Kai Lin

IPC: H01L29/92 ,  H01L27/108 ,  H01L27/105

CPC classification number: H01L27/10817 ,  H01L27/105 ,  H01L27/10852 ,  H01L28/91

Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.

Abstract translation: 电容器阵列包括多个电容器和支撑框架。 每个电容器包括电极。 支撑框架支撑多个电极，并且包括对应于多个电极的多个支撑结构。 每个支撑结构可以围绕相应的电极。 支撑框架可以包括掺杂可氧化材料的氧化物。

公开(公告)号：US08497541B2

公开(公告)日：2013-07-30

申请号：US12721404

申请日：2010-03-10

Applicant: Kunal Parekh ,  David Hwang ,  Wen Kuei Huang ,  Kuo Chen Wang ,  Ching Kai Lin

Inventor： Kunal Parekh ,  David Hwang ,  Wen Kuei Huang ,  Kuo Chen Wang ,  Ching Kai Lin

IPC: H01L27/108

CPC classification number: G11C5/06 ,  G11C5/025 ,  G11C11/405 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10879 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785

Abstract: A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.

Abstract translation: 具有存储单元的存储器阵列及其形成方法。 存储器阵列可以具有形成在第一水平平面体积中的掩埋数字线，形成在第一水平平面体积上方的第二水平平面体积中的字线和形成在垂直存取装置（例如finFET）的顶部上的存储装置， 在第二水平平面体积之上的第三水平平面体积。 存储器阵列可以具有4F2架构，其中每个存储器单元包括两个垂直存取设备，每个垂直存取设备耦合到单个存储设备。

公开(公告)号：US06183940B2

公开(公告)日：2001-02-06

申请号：US09040480

申请日：1998-03-17

Applicant: Chen-Yu Wang ,  Tseng You Syau ,  Ching-Kai Lin

Inventor： Chen-Yu Wang ,  Tseng You Syau ,  Ching-Kai Lin

IPC: G03F700

CPC classification number: G03F7/40 ,  C23F1/02 ,  C23F4/00 ,  H01L21/0274 ,  H01L21/0276 ,  H01L21/32139

Abstract: A method of retaining the integrity of a photoresist pattern is provided where the patterned photoresist is treated prior to etching the principle layer. The pre-etch treatment encompasses a plasma treatment. In some embodiments employing an anti-reflective coating (ARC) layer, an isolation/protective layer is used to isolate the ARC from the photoresist. In some embodiments, the pre-etch treatment, advantageously provides for patterning the isolation/protection layer.

Abstract translation: 提供了保留光致抗蚀剂图案的完整性的方法，其中在蚀刻原理层之前处理图案化的光致抗蚀剂。 预蚀刻处理包括等离子体处理。 在采用抗反射涂层（ARC）层的一些实施例中，隔离/保护层用于将ARC与光致抗蚀剂隔离。 在一些实施例中，预蚀刻处理有利地提供图案化隔离/保护层。

公开(公告)号：US20130161786A1

公开(公告)日：2013-06-27

申请号：US13333564

申请日：2011-12-21

Applicant: Jen Jui Huang ,  Che Chi Lee ,  Shih Shu Tsai ,  Cheng Shun Chen ,  Shao Ta Hsu ,  Chao Wen Lay ,  Chun I. Hsieh ,  Ching Kai Lin

Inventor： Jen Jui Huang ,  Che Chi Lee ,  Shih Shu Tsai ,  Cheng Shun Chen ,  Shao Ta Hsu ,  Chao Wen Lay ,  Chun I. Hsieh ,  Ching Kai Lin

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L27/10817 ,  H01L27/105 ,  H01L27/10852 ,  H01L28/91

Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.

Abstract translation: 电容器阵列包括多个电容器和支撑框架。 每个电容器包括电极。 支撑框架支撑多个电极，并且包括对应于多个电极的多个支撑结构。 每个支撑结构可以围绕相应的电极。 支撑框架可以包括掺杂可氧化材料的氧化物。

公开(公告)号：US08420208B2

公开(公告)日：2013-04-16

申请号：US12854734

申请日：2010-08-11

Applicant: Tsai-Yu Huang ,  Ching-Kai Lin

Inventor： Tsai-Yu Huang ,  Ching-Kai Lin

IPC: B32B5/00 ,  C01G23/047 ,  C23C16/00

CPC classification number: H01L21/02186 ,  H01L21/022 ,  H01L21/0228 ,  H01L28/40

Abstract: A method of forming a high-k dielectric material including forming at least two portions of titanium dioxide, the at least two portions of titanium dioxide comprising a first portion comprising amorphous titanium dioxide and a second portion comprising rutile titanium dioxide. A method of forming a high-k dielectric material including forming a first portion of titanium dioxide at a temperature of from about 150° C. to about 350° C. and forming a second portion of titanium dioxide at a temperature of from about 350° C. to about 600° C. A high-k dielectric material is also disclosed.

Abstract translation: 一种形成高k电介质材料的方法，包括形成二氧化钛的至少两部分，二氧化钛的至少两部分包括包含无定形二氧化钛的第一部分和包含金红石型二氧化钛的第二部分。 一种形成高k介电材料的方法，包括在约150℃至约350℃的温度下形成二氧化钛的第一部分，并在约350℃的温度下形成第二部分二氧化钛 C.至约600℃。还公开了高k电介质材料。

公开(公告)号：US08222163B2

公开(公告)日：2012-07-17

申请号：US12851561

申请日：2010-08-06

Applicant: Chao-Wen Lay ,  Ching-Kai Lin

Inventor： Chao-Wen Lay ,  Ching-Kai Lin

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/302 ,  H01L21/02238 ,  H01L21/30604

Abstract: A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore, a method of flattening a recess in a substrate is provided. The method includes: first, providing a substrate having a trench therein, wherein the trench has a sidewall comprising a recessed section and an unrecessed section. Then, a recessed section oxidation rate change step is performed to change an oxidation rate of the recessed section. Later, an oxidizing process is performed to the substrate so as to form a first oxide layer on the recessed section, and a second oxide layer on the unrecessed section, wherein the second oxide layer is thicker than the first oxide layer. Finally, the first oxide layer and the second oxide layer are removed to form a flattened sidewall of the trench.

Abstract translation: 由于干蚀刻，凹槽通常形成在沟槽的侧壁上。 凹槽可影响形成在沟槽中的元件的轮廓。 因此，提供了在基板中使凹部变平的方法。 该方法包括：首先，提供其中具有沟槽的衬底，其中沟槽具有包括凹陷部分和未加工部分的侧壁。 然后，进行凹部氧化速度变化步骤，以改变凹部的氧化速率。 然后，对基板进行氧化处理，以在凹部上形成第一氧化物层，在未加工部分上形成第二氧化物层，其中第二氧化物层比第一氧化物层厚。 最后，去除第一氧化物层和第二氧化物层以形成沟槽的扁平侧壁。

公开(公告)号：US20120034791A1

公开(公告)日：2012-02-09

申请号：US12851561

申请日：2010-08-06

Applicant: Chao-Wen Lay ,  Ching-Kai Lin

Inventor： Chao-Wen Lay ,  Ching-Kai Lin

IPC: H01L21/316

CPC classification number: H01L21/302 ,  H01L21/02238 ,  H01L21/30604

Abstract: A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore, a method of flattening a recess in a substrate is provided. The method includes: first, providing a substrate having a trench therein, wherein the trench has a sidewall comprising a recessed section and an unrecessed section. Then, a recessed section oxidation rate change step is performed to change an oxidation rate of the recessed section. Later, an oxidizing process is performed to the substrate so as to form a first oxide layer on the recessed section, and a second oxide layer on the unrecessed section, wherein the second oxide layer is thicker than the first oxide layer. Finally, the first oxide layer and the second oxide layer are removed to form a flattened sidewall of the trench.

Abstract translation: 由于干蚀刻，凹槽通常形成在沟槽的侧壁上。 凹槽可影响形成在沟槽中的元件的轮廓。 因此，提供了在基板中使凹部变平的方法。 该方法包括：首先，提供其中具有沟槽的衬底，其中沟槽具有包括凹陷部分和未加工部分的侧壁。 然后，进行凹部氧化速度变化步骤，以改变凹部的氧化速率。 然后，对基板进行氧化处理，以在凹部上形成第一氧化物层，在未加工部分上形成第二氧化物层，其中第二氧化物层比第一氧化物层厚。 最后，去除第一氧化物层和第二氧化物层以形成沟槽的扁平侧壁。

公开(公告)号：US20110220980A1

公开(公告)日：2011-09-15

申请号：US12721404

申请日：2010-03-10

Applicant: Kunal Parekh ,  David Hwang ,  Wen Kuei Huang ,  Kuo Chen Wang ,  Ching Kai Lin

Inventor： Kunal Parekh ,  David Hwang ,  Wen Kuei Huang ,  Kuo Chen Wang ,  Ching Kai Lin

IPC: H01L27/108 ,  H01L21/336

CPC classification number: G11C5/06 ,  G11C5/025 ,  G11C11/405 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10879 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785

Abstract: A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.

Abstract translation: 具有存储单元的存储器阵列及其形成方法。 存储器阵列可以具有形成在第一水平平面体积中的掩埋数字线，形成在第一水平平面体积上方的第二水平平面体积中的字线和形成在垂直存取装置（例如finFET）的顶部上的存储装置， 在第二水平平面体积之上的第三水平平面体积。 存储器阵列可以具有4F2架构，其中每个存储器单元包括两个垂直存取设备，每个垂直存取设备耦合到单个存储设备。

公开(公告)号：US06342670B1

公开(公告)日：2002-01-29

申请号：US09664780

申请日：2000-09-19

Applicant: Ching Kai Lin ,  Hsu Keng Tseng

Inventor： Ching Kai Lin ,  Hsu Keng Tseng

IPC: H01L31048

CPC classification number: H01L31/0203 ,  G08C23/04 ,  H01L31/02327 ,  H01L31/167 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/1815 ,  Y10S136/293 ,  Y10S362/80 ,  Y10S428/901 ,  H01L2924/00014

Abstract: A photoelectric module device comprising a multiple layer printed circuit board and at least one photoelectric module device is provided. The multiple layer printed circuit board has at least an upper circuit board substrate, a lower circuit board substrate, and a circuit. A plurality of photoelectric elements are installed on the multiple layer printed circuit board and is electrically connected to the circuit. The photoelectric elements are packaged above the multiple layer printed circuit board by injection molding a transparent resin thereon. The lower substrate has a plurality of through holes formed therein and the inner wall of the through holes is plated with metal, as an electric terminal. The upper circuit board substrate serves to seal the through holes and prevent resin from permeating therein during the injection molding process. When the circuit board is cut into separate photoelectric module devices, after packaging, the inner wall of the through holes are partially cut away and the remaining portion thereof becomes a terminal for electrically connecting to external devices.

Abstract translation: 提供一种包括多层印刷电路板和至少一个光电模块装置的光电模块装置。 多层印刷电路板至少具有上电路板基板，下电路板基板和电路。 多个光电元件安装在多层印刷电路板上，并与电路电连接。 光电元件通过在其上注塑成型透明树脂而封装在多层印刷电路板的上方。 下基板具有形成在其中的多个通孔，并且通孔的内壁镀有金属作为电端子。 上部电路板基板用于密封通孔，并防止树脂在注射成型过程中渗入其中。 当将电路板切割成单独的光电模块装置时，在封装之后，通孔的内壁被部分地切除，其余部分变成用于电连接到外部装置的端子。

公开(公告)号：US20120040162A1

公开(公告)日：2012-02-16

申请号：US12854734

申请日：2010-08-11

Applicant: Tsai-Yu Huang ,  Ching-Kai Lin

Inventor： Tsai-Yu Huang ,  Ching-Kai Lin

IPC: B32B18/00 ,  H01L21/314 ,  C01G23/047

CPC classification number: H01L21/02186 ,  H01L21/022 ,  H01L21/0228 ,  H01L28/40

Abstract: A method of forming a high-k dielectric material including forming at least two portions of titanium dioxide, the at least two portions of titanium dioxide comprising a first portion comprising amorphous titanium dioxide and a second portion comprising rutile titanium dioxide. A method of forming a high-k dielectric material including forming a first portion of titanium dioxide at a temperature of from about 150° C. to about 350° C. and forming a second portion of titanium dioxide at a temperature of from about 350° C. to about 600° C. A high-k dielectric material is also disclosed.

Abstract translation: 一种形成高k电介质材料的方法，包括形成二氧化钛的至少两部分，二氧化钛的至少两部分包括包含无定形二氧化钛的第一部分和包含金红石型二氧化钛的第二部分。 一种形成高k介电材料的方法，包括在约150℃至约350℃的温度下形成二氧化钛的第一部分，并在约350℃的温度下形成第二部分二氧化钛 C.至约600℃。还公开了高k电介质材料。