公开(公告)号：US08791504B2

公开(公告)日：2014-07-29

申请号：US13277692

申请日：2011-10-20

Applicant: Chi-Ming Chen ,  Po-Chun Liu ,  Hung-Ta Lin ,  Chin-Cheng Chang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

Inventor： Chi-Ming Chen ,  Po-Chun Liu ,  Hung-Ta Lin ,  Chin-Cheng Chang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

IPC: H01L29/66

CPC classification number: H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7787

Abstract: A circuit structure includes a substrate, a nucleation layer of undoped aluminum nitride, a graded buffer layer comprising aluminum, gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant, a ungraded buffer layer comprising gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant without aluminum, and a bulk layer of undoped gallium nitride over the ungraded buffer layer. The various dopants in the graded buffer layer and the ungraded buffer layer increases resistivity and results in layers having an intrinsically balanced conductivity.

Abstract translation: 电路结构包括衬底，未掺杂的氮化铝的成核层，包含铝，镓，氮，硅和氧中的一种的梯度缓冲层和p型导电掺杂剂，包含镓，氮，一个 的硅和氧，以及没有铝的p型导电掺杂物，以及未分级缓冲层上的未掺杂氮化镓的体层。 分级缓冲层和未分级缓冲层中的各种掺杂剂增加了电阻率并导致具有本质上平衡的导电性的层。

公开(公告)号：US08772831B2

公开(公告)日：2014-07-08

申请号：US13290534

申请日：2011-11-07

Applicant: Chi-Ming Chen ,  Po-Chun Liu ,  Hung-Ta Lin ,  Chin-Cheng Chang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

Inventor： Chi-Ming Chen ,  Po-Chun Liu ,  Hung-Ta Lin ,  Chin-Cheng Chang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

IPC: H01L29/267 ,  H01L29/778

CPC classification number: H01L33/007 ,  C30B25/183 ,  C30B29/403 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/2003 ,  H01L29/66462

Abstract: A circuit structure includes a substrate and a patterned dielectric layer over the substrate. The patterned dielectric layer includes a plurality of vias; and a number of group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layers include a first layer in the vias, a second layer over the first layer and the dielectric layer, and a bulk layer over the second layer.

Abstract translation: 电路结构包括衬底和衬底上的图案化电介质层。 图案化电介质层包括多个通孔; 和III族V族（III-V）族化合物半导体层。 III-V族化合物半导体层包括通孔中的第一层，第一层上的第二层和电介质层，以及在第二层上的体层。

公开(公告)号：US20120149176A1

公开(公告)日：2012-06-14

申请号：US12964994

申请日：2010-12-10

Applicant: Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

Inventor： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

IPC: H01L21/20 ,  C23C16/34

CPC classification number: C23C16/303 ,  C23C16/4401 ,  C23C16/54 ,  C23C16/56

Abstract: Provided is an apparatus. The apparatus includes: a first deposition component that is operable to form a compound over a semiconductor wafer, the compound including at least one of: a III-family element and a V-family element; a second deposition component that is operable to form a passivation layer over the compound; and a transfer component that is operable to move the semiconductor wafer between the first and second deposition components, the transfer component enclosing a space that contains substantially no oxygen and substantially no silicon; wherein the loading component, the first and second deposition components, and the transfer component are all integrated into a single fabrication tool.

Abstract translation: 提供了一种装置。 该装置包括：第一沉积部件，其可操作以在半导体晶片上形成化合物，所述化合物包括III族元素和V族元素中的至少一种; 第二沉积组分，其可操作以在所述化合物上形成钝化层; 以及可操作以在所述第一和第二沉积部件之间移动所述半导体晶片的转移部件，所述转移部件包围基本上不含氧且基本上不含硅的空间; 其中装载部件，第一和第二沉积部件以及传送部件都被集成到单个制造工具中。

公开(公告)号：US08090013B2

公开(公告)日：2012-01-03

申请号：US12043751

申请日：2008-03-06

Applicant: Arash Farhoodfar ,  Kishore Kota ,  Alan Kwentus ,  David Hwang

Inventor： Arash Farhoodfar ,  Kishore Kota ,  Alan Kwentus ,  David Hwang

IPC: H03H7/30 ,  H04B15/00 ,  H04N5/00

CPC classification number: H04L25/497 ,  H04L25/4975

Abstract: Herein described are at least a method and a system for implementing a high speed Tomlinson-Harashima Precoder. The method comprises using an L-tap transpose configuration of a Tomlinson-Harashima Precoder and processing a first discrete time sampled sequence using said L coefficients and L state variables by clocking the L-tap Tomlinson-Harashima Precoder using a clock signal wherein the clock signal has a clock rate equal to one half the symbol rate of the discrete time sampled sequence. In a representative embodiment, an L-tap Tomlinson-Harashima Precoder comprises a single integrated circuit chip, wherein the integrated circuit chip comprises at least one circuitry for processing a discrete time sampled sequence using L coefficients and L state variables by way of clocking the discrete time sampled sequence using a clock signal having a clock rate that is one half the symbol rate of the discrete time sampled sequence.

Abstract translation: 这里描述了至少一种用于实现高速Tomlinson-Harashima Precoder的方法和系统。 该方法包括使用Tomlinson-Harashima预编码器的L抽头转置配置，并使用时钟信号对所述L系数和L状态变量进行处理，以便使用L抽头Tomlinson-Harashima Precoder，其中时钟信号 具有等于​​离散时间采样序列的符号速率的一半的时钟速率。 在代表性实施例中，L抽头Tomlinson-Harashima预编码器包括单个集成电路芯片，其中该集成电路芯片包括至少一个电路，用于通过使用离散的时钟来处理使用L个系数和L个状态变量的离散时间采样序列 使用时钟速率为离散时间采样序列的符号率的一半的时钟信号的时间采样序列。

公开(公告)号：US20110140187A1

公开(公告)日：2011-06-16

申请号：US13036725

申请日：2011-02-28

Applicant: Larson Lindholm ,  David Hwang

Inventor： Larson Lindholm ,  David Hwang

IPC: H01L27/108 ,  H01L21/8242 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L27/0207 ,  H01L27/10876 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/7827

Abstract: A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated.

Abstract translation: 形成垂直场效应晶体管的方法包括将开口蚀刻成半导体材料。 开口底座的侧壁和径向最外部的部分衬有掩模材料。 半导体材料柱外延生长在与开口底部的半导体材料的掩模材料相邻的开口内。 至少一些掩模材料从开口去除。 栅极电介质围绕柱径向地形成。 导电栅极材料围绕栅极电介质径向地形成。 柱的上部形成为包括垂直晶体管的一个源极/漏极区域。 接收在上部下方的柱的半导体材料形成为包括垂直晶体管的沟道区。 与开口相邻的半导体材料形成为包括垂直晶体管的另一个源极/漏极区域。 考虑了其他方面和实现。

公开(公告)号：US07329810B2

公开(公告)日：2008-02-12

申请号：US11255984

申请日：2005-10-24

Applicant: Larry Spivack ,  Noah David Hwang ,  Glen Ayers

Inventor： Larry Spivack ,  Noah David Hwang ,  Glen Ayers

IPC: G10D13/02

CPC classification number: G10D13/065

Abstract: A percussion instrument includes a stand, an operating rod defining a first axis, a foot pedal operably associated with the operating rod for permitting movement of the operating rod along the first axis, and a pair of movable arms coupled to the stand. A first rigid vibrator is disposed on one of the arms and a second rigid vibrator is disposed on the other of the arms. A clutch is coupled to the arms for governing movement thereof, wherein the arms are rotatable toward each other and toward the first axis.

Abstract translation: 打击乐器包括支架，限定第一轴线的操作杆，与操作杆可操作地相关联的用于允许操作杆沿着第一轴线移动的脚踏板，以及联接到支架的一对可动臂。 第一刚性振动器设置在一个臂上，第二刚性振动器设置在另一个臂上。 离合器联接到臂上用于控制其运动，其中臂可朝向彼此旋转并且朝向第一轴线旋转。

公开(公告)号：US20060263969A1

公开(公告)日：2006-11-23

申请号：US11132472

申请日：2005-05-19

Applicant: David Hwang ,  Kunal Parekh ,  Michael Willett ,  Jigish Trivedi ,  Suraj Mathew ,  Greg Peterson

Inventor： David Hwang ,  Kunal Parekh ,  Michael Willett ,  Jigish Trivedi ,  Suraj Mathew ,  Greg Peterson

IPC: H01L21/8244

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11543

Abstract: The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.

公开(公告)号：US07026834B2

公开(公告)日：2006-04-11

申请号：US11222286

申请日：2005-09-08

Applicant: David Hwang

Inventor： David Hwang

IPC: G01R31/26

CPC classification number: G01R1/0416

Abstract: A novel probe block assembly which independently floats multiple probe blocks in a single frame is presented. The independently floating probe blocks allow multiple probes to align independently with respective multiple mating features on a device under test. The use of a single frame allows multiple insertion probe testing via one actuation motion.

Abstract translation: 提出了一种在单个框架中独立浮动多个探针块的新型探针块组件。 独立浮动探头块允许多个探头独立地对准被测器件上的相应多个匹配特征。 使用单个框架允许通过一个致动运动进行多次插入探针测试。

公开(公告)号：US08723185B2

公开(公告)日：2014-05-13

申请号：US12956145

申请日：2010-11-30

Applicant: Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

Inventor： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

IPC: H01L29/20 ,  H01L21/20 ,  H01L21/18

CPC classification number: H01L21/0254 ,  H01L21/02365 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02458 ,  H01L21/02658 ,  H01L29/66446 ,  H01L29/66522 ,  H01L33/007

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括提供具有相对的第一和第二侧面的硅衬底。 第一和第二面中的至少一个包括硅（111）表面。 该方法包括在硅衬底的第一侧上形成高的热膨胀系数（CTE）层。 高CTE层的CTE大于硅的CTE。 该方法包括在硅衬底的第二侧上形成缓冲层。 缓冲层的CTE大于硅的CTE。 该方法包括在缓冲层上形成III-V族层。 III-V族层的CTE大于缓冲层的CTE。

公开(公告)号：US08624326B2

公开(公告)日：2014-01-07

申请号：US13277669

申请日：2011-10-20

Applicant: Chi-Ming Chen ,  Chung-Yi Yu ,  Ho-Yung David Hwang

Inventor： Chi-Ming Chen ,  Chung-Yi Yu ,  Ho-Yung David Hwang

IPC: H01L21/70

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first dielectric layer disposed over the substrate. The semiconductor device further includes a buffer layer disposed over the substrate and between first and second walls of a trench of the dielectric layer. The semiconductor device further includes an insulator layer disposed over the buffer layer and between the first and second wall of the trench of the dielectric layer. The semiconductor device also includes a second dielectric layer disposed over the first dielectric layer and the insulator layer. Further, the semiconductor device includes a fin structure disposed over the insulator layer and between first and second walls of a trench of the second dielectric layer.

Abstract translation: 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括：衬底，包括设置在衬底上的第一介电层。 该半导体器件还包括一个缓冲层，该缓冲层设置在该衬底上并且位于介电层沟槽的第一和第二壁之间。 半导体器件还包括设置在缓冲层之上并位于介电层沟槽的第一和第二壁之间的绝缘体层。 半导体器件还包括设置在第一介电层和绝缘体层之上的第二电介质层。 此外，半导体器件包括布置在绝缘体层之上以及第二介电层的沟槽的第一和第二壁之间的翅片结构。