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42 条记录 (耗时 0.017 秒)

    Method of manufacturing sidewall spacers on a memory device, and device comprising same
    1.
    发明授权
    Method of manufacturing sidewall spacers on a memory device, and device comprising same 有权

    公开(公告)号：US07341906B2

    公开(公告)日：2008-03-11

    申请号：US11132472

    申请日：2005-05-19

    申请人： David K. Hwang ,  Kunal Parekh ,  Michael Willett ,  Jigish Trivedi ,  Suraj Mathew ,  Greg Peterson

    发明人： David K. Hwang ,  Kunal Parekh ,  Michael Willett ,  Jigish Trivedi ,  Suraj Mathew ,  Greg Peterson

    IPC分类号： H01L21/8244

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11543

    摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.

    Dual depth trench isolation
    4.
    发明申请
    Dual depth trench isolation 审中-公开

    公开(公告)号：US20060043522A1

    公开(公告)日：2006-03-02

    申请号：US11097021

    申请日：2005-03-31

    申请人： Jigish Trivedi

    发明人： Jigish Trivedi

    IPC分类号： H01L29/00

    CPC分类号： H01L21/76229

    摘要： A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structure having a second isolation trench depth which combine to form a dual depth trench containing the dual depth trench isolation structure comprising the first inter-well isolation structure and the second inter-well isolation structure, with the dual depth trench isolation interposed at the boundary of an n-well conductive region and a p-well conductive region, a first intra-well isolation structure having a first isolation trench depth, the first intra-well isolation structure interposed between a pair of p-channel transistors residing in the n-well region, and a second intra-well isolation structure having a second isolation trench depth, the second intra-well isolation structure interposed between a pair of n-channel transistors residing in the p-well region.

    Memory devices
    5.
    发明申请
    Memory devices 审中-公开
    内存设备

    公开(公告)号：US20050156273A1

    公开(公告)日：2005-07-21

    申请号：US11079974

    申请日：2005-03-14

    申请人： Jigish Trivedi

    发明人： Jigish Trivedi

    IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L21/76 ,  H01L23/48 ,  H01L29/00

    CPC分类号： H01L21/76895 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a local interconnect includes forming an isolation trench within a semiconductor substrate. A first trench isolation material is deposited to within the trench. First isolation material is removed effective to form a line trench into a desired local interconnect. Conductive material is formed therewithin. A second isolation material is deposited over the first isolation material, over the conductive material within the isolation trench and within the line trench. At least some first and second isolation material is removed in at least one common removing step. Integrated circuitry includes a substrate comprising trench isolation material. A local interconnect line is received within a trench formed within the isolation material. The local interconnect includes at least two different conductive materials. One of the conductive materials lines the trench. Another of the conductive materials is received within a conductive trench formed by the one. Other implementations are disclosed.

    摘要翻译： 形成局部互连的方法包括在半导体衬底内形成隔离沟槽。 第一沟槽隔离材料沉积到沟槽内。 去除有效的第一隔离材料以将线沟槽形成所需的局部互连。 在其中形成导电材料。 第二隔离材料沉积在第一隔离材料之上，在隔离沟槽内部和导线沟槽内的导电材料上。 至少一些第一和第二隔离材料在至少一个常见的去除步骤中被去除。 集成电路包括包括沟槽隔离材料的衬底。 局部互连线接收在形成在隔离材料内的沟槽内。 局部互连包括至少两种不同的导电材料。 导电材料之一将沟槽排列。 另一种导电材料被接收在由该导电材料形成的导电沟槽内。 公开了其他实现。

    Semiconductor fuses, methods of using the same, methods of making the same, and semiconductor devices containing the same
    7.
    发明授权
    Semiconductor fuses, methods of using the same, methods of making the same, and semiconductor devices containing the same 有权
    半导体熔丝，其使用方法，制造方法以及包含该半导体熔丝的半导体器件

    公开(公告)号：US06277674B1

    公开(公告)日：2001-08-21

    申请号：US09165754

    申请日：1998-10-02

    申请人： Zhongze Wang ,  Michael P. Violette ,  Jigish Trivedi

    发明人： Zhongze Wang ,  Michael P. Violette ,  Jigish Trivedi

    IPC分类号： H01L2182

    CPC分类号： H01L21/76888 ,  H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers—an overlying and underlying layer—on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

    摘要翻译： 用于集成电路和半导体器件的保险丝，其制造方法，使用该保险丝的方法以及包含该保险丝的半导体器件。 半导体熔丝在绝缘基板上包含两层导电层 - 覆盖层和下层。 底层包括氮化钛，上覆层包括硅化钨。 半导体保险丝可以在制造包含相同材料的局部互连结构时制造。 可用于编程冗余电路的保险丝由电流而不是激光束吹扫，从而允许熔丝宽度小于由激光束吹制的现有技术的熔丝。 熔断器也可能被吹过比吹出具有相似尺寸的常规多晶硅保险丝所需的电流更小的电流。

    METHOD OF MANUFACTURING SIDEWALL SPACERS ON A MEMORY DEVICE, AND DEVICE COMPRISING SAME
    9.
    发明申请
    METHOD OF MANUFACTURING SIDEWALL SPACERS ON A MEMORY DEVICE, AND DEVICE COMPRISING SAME 有权
    在存储器件上制造隔板间隔的方法以及包含其的装置

    公开(公告)号：US20080119053A1

    公开(公告)日：2008-05-22

    申请号：US12020752

    申请日：2008-01-28

    申请人： David Hwang ,  Kunal Parekh ,  Michael Willett ,  Jigish Trivedi ,  Suraj Mathew ,  Greg Peterson

    发明人： David Hwang ,  Kunal Parekh ,  Michael Willett ,  Jigish Trivedi ,  Suraj Mathew ,  Greg Peterson

    IPC分类号： H01L21/311

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11543

    摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.

    摘要翻译： 本发明一般涉及在存储器件上制造侧壁间隔物的方法，以及包括这种侧壁间隔物的存储器件。 在一个说明性实施例中，该方法包括在由存储器阵列和至少一个外围电路构成的存储器件上形成侧壁间隔物，该隔离物通过形成邻近存储器阵列中的字线结构的第一侧壁间隔物，第一侧壁间隔物具有第一厚度 以及在所述外围电路中形成与所述晶体管结构相邻的第二侧壁间隔物，所述第二侧壁间隔物具有大于所述第一厚度的第二厚度，其中所述第一和第二侧壁间隔物包括来自单层间隔物材料的材料。 在一个说明性实施例中，该装置包括由多个字线结构组成的存储器阵列，多个字线结构中的每一个具有与其相邻形成的第一侧壁间隔物，第一侧壁间隔物具有第一厚度，外围电路 包括至少一个晶体管，其具有与其相邻形成的第二侧壁间隔物，所述第二侧壁间隔物具有大于第一厚度的第二厚度，所述第一和第二侧壁间隔物由来自单层间隔物材料的材料构成。

    METHODS FOR FORMING SHALLOW TRENCH ISOLATION
    10.
    发明申请
    METHODS FOR FORMING SHALLOW TRENCH ISOLATION 有权
    形成浅层分离的方法

    公开(公告)号：US20070004131A1

    公开(公告)日：2007-01-04

    申请号：US11470150

    申请日：2006-09-05

    申请人： Jigish Trivedi ,  Robert Patraw ,  Kevin Beaman ,  John Smythe

    发明人： Jigish Trivedi ,  Robert Patraw ,  Kevin Beaman ,  John Smythe

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/76224 ,  H01L21/76227

    摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.

    摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面蚀刻沟槽之后，将氮化硅屏障沉积到沟槽中。 氮化硅层在沟壁附近具有高氮含量以保护壁。 进一步从沟槽壁的氮化硅层具有低的氮含量和高的硅含量，以提高粘附性。 然后用旋涂前体填充沟槽。 然后施加致密化或反应过程以将旋涂材料转化成绝缘体。 所得的沟槽具有良好粘附的绝缘体，其有助于沟槽的绝缘性能。