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    PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE
    5.
    发明申请
    PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE 有权
    相位变化记忆体与调制结构

    公开(公告)号：US20090231911A1

    公开(公告)日：2009-09-17

    申请号：US12049056

    申请日：2008-03-14

    申请人： Jun Liu ,  Michael P. Violette

    发明人： Jun Liu ,  Michael P. Violette

    IPC分类号： G11C11/00 ,  H01L47/00 ,  H01L21/00

    CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1683

    摘要： Some embodiments include apparatus and methods having a memory cell with a first electrode and a second electrode, and a memory element directly contacting the first and second electrodes. The memory element may include a programmable portion having a material configured to change between multiple phases. The programmable portion may be isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element.

    摘要翻译： 一些实施例包括具有具有第一电极和第二电极的存储单元的设备和方法，以及直接接触第一和第二电极的存储元件。 存储元件可以包括具有被配置为在多个相之间变化的材料的可编程部分。 可编程部分可以通过存储元件的第一部分与第一电极隔离，并且通过存储元件的第二部分与第二电极隔离。

    Semiconductor fuses and semiconductor devices containing the same
    7.
    发明授权
    Semiconductor fuses and semiconductor devices containing the same 失效
    半导体保险丝和含有其的半导体器件

    公开(公告)号：US06927473B2

    公开(公告)日：2005-08-09

    申请号：US10620054

    申请日：2003-07-14

    申请人： Zhongze Wang ,  Michael P. Violette ,  Jigish Trivedi

    发明人： Zhongze Wang ,  Michael P. Violette ,  Jigish Trivedi

    IPC分类号： H01L23/525 ,  H01L29/00

    CPC分类号： H01L21/76888 ,  H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Fuses for integrated circuits and semiconductor devices, methods for making and using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers, an overlying and underlying layer, on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

    摘要翻译： 用于集成电路和半导体器件的保险丝，其制造和使用的方法以及包含该保险丝的半导体器件。 半导体熔丝在绝缘基板上包含两层导电层，一层覆盖和下层。 底层包括氮化钛，上覆层包括硅化钨。 半导体保险丝可以在制造包含相同材料的局部互连结构时制造。 可用于编程冗余电路的保险丝由电流而不是激光束吹扫，从而允许熔丝宽度小于由激光束吹制的现有技术的熔丝。 熔断器也可能被吹过比吹出具有相似尺寸的常规多晶硅保险丝所需的电流更小的电流。

    Fuse for use in a semiconductor device, and semiconductor devices including the fuse
    8.
    发明授权
    Fuse for use in a semiconductor device, and semiconductor devices including the fuse 有权

    公开(公告)号：US06495902B2

    公开(公告)日：2002-12-17

    申请号：US09943993

    申请日：2001-08-30

    申请人： Kenneth W. Marr ,  Michael P. Violette

    发明人： Kenneth W. Marr ,  Michael P. Violette

    IPC分类号： H01L2900

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region located between the terminal region and the conductive region and positioned adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse “blows” at the narrowed region. The diode or diodes between wells of different conductivity types wells and the Schottky diode or diodes between the remaining portions of the fuse and wells adjacent thereto control the flow of current through the remainder of the fuse and through the associated wells of the semiconductor device. When the fuse has been “blown,” the diodes and Schottky diodes prevent current of a normal operating voltage from flowing through the wells of the semiconductor device.

    Fuse for use in a semiconductor device
    9.
    发明授权
    Fuse for use in a semiconductor device 失效
    用于半导体器件的保险丝和包括保险丝的半导体器件

    公开(公告)号：US06323534B1

    公开(公告)日：2001-11-27

    申请号：US09293192

    申请日：1999-04-16

    申请人： Kenneth W. Marr ,  Michael P. Violette

    发明人： Kenneth W. Marr ,  Michael P. Violette

    IPC分类号： H01L2900

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal silicide fuse for a semiconductor device. A conductive region of the fuse may be disposed adjacent a common well of semiconductive material of a first conductivity type. A terminal region of the fuse may be disposed adjacent a well of semiconductive material of a second conductivity type. A narrowed region of the fuse, which is disposed between the terminal region and the conductive region, is disposed adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse preferably “blows” at the narrowed region. The diode or diodes between the different conductivity type wells and the Schottky diode or diodes between the remaining portions of the fuse and adjacent wells of the semiconductor device control the flow of current through the remainder of the fuse and through the adjacent conductive wells of the semiconductor device. Thus, if the fuse “blows” as desired, the diodes and Schottky diodes formed by the fuse and the adjacent conductive wells will prevent current at a normal operating voltage from flowing through the conductive wells of the semiconductor device. The present invention also includes methods of fabricating a fuse.

    摘要翻译： 一种用于半导体器件的金属硅化物熔断器。 保险丝的导电区域可以邻近第一导电类型的半导体材料的公共孔布置。 保险丝的端子区域可以邻近第二导电类型的半导体材料的孔设置。 设置在端子区域和导电区域之间的保险丝的窄区域邻近两个阱之间的边界设置。 当至少对保险丝施加编程电流时，保险丝优选地在变窄的区域“吹”。 不同导电类型阱之间的二极管或二极管与保险丝的剩余部分和半导体器件的相邻阱之间的肖特基二极管或二极管控制通过保险丝的其余部分的电流的流动并通过半导体的相邻导电阱 设备。 因此，如果熔丝根据需要“吹”，由熔丝和相邻导电阱形成的二极管和肖特基二极管将防止在正常工作电压下的电流流过半导体器件的导电阱。 本发明还包括制造保险丝的方法。

    Method of isolating a SRAM cell
    10.
    发明授权
    Method of isolating a SRAM cell 失效
    隔离SRAM单元的方法

    公开(公告)号：US06301148B1

    公开(公告)日：2001-10-09

    申请号：US09542629

    申请日：2000-04-04

    申请人： Michael P. Violette

    发明人： Michael P. Violette

    IPC分类号： G11C1100

    CPC分类号： H01L21/76202

    摘要： A static random access memory cell comprising a first invertor including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second invertor including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first invertor being cross-coupled with the second invertor, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first invertor; a second access transistor having an active terminal connected to the second invertor; and an isolator isolating the first pullup transistor from the second pullup transistor.

    摘要翻译： 一种包括第一反相器的静态随机存取存储单元，包括第一p沟道上拉晶体管和与第一p沟道上拉晶体管串联的第一n沟道下拉晶体管; 包括第二p沟道上拉晶体管的第二反相器和与所述第二n沟道上拉晶体管串联的第二n沟道下拉晶体管，所述第一反相器与所述第二反相器交叉耦合，所述第一和第二上拉晶体管共享 一个共同的活跃区域; 第一存取晶体管，具有连接到第一反相器的有源端子; 第二存取晶体管，具有连接到第二反相器的有源端子; 以及将所述第一上拉晶体管与所述第二上拉晶体管隔离的隔离器。