公开(公告)号：US20140080259A1

公开(公告)日：2014-03-20

申请号：US13621540

申请日：2012-09-17

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima ,  Ryuji Fujii

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima ,  Ryuji Fujii

IPC: H01L21/82

CPC classification number: H01L24/96 ,  H01L21/6835 ,  H01L22/22 ,  H01L24/24 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2224/03 ,  H01L2224/83

Abstract: In a manufacturing method for layered chip packages, a layered substructure with at least one additional package joined thereto is used to produce a plurality of layered chip packages. The layered substructure includes a plurality of main bodies to be separated from each other later. Each main body includes: a main part having top and bottom surfaces and including a plurality of layer portions stacked on each other; and a plurality of main terminals disposed on at least one of the top and bottom surfaces of the main part. The additional package includes an additional semiconductor chip and at least one additional terminal that is electrically connected to the additional semiconductor chip and in contact with at least one of the plurality of main terminals.

Abstract translation: 在层叠芯片封装的制造方法中，使用具有与其连接的至少一个附加封装的分层子结构来制造多个分层芯片封装。 分层子结构包括稍后要彼此分离的多个主体。 每个主体包括：具有顶表面和底表面并且包括彼此堆叠的多个层部分的主要部分; 以及设置在主要部件的顶表面和底表面中的至少一个上的多个主端子。 附加封装包括附加的半导体芯片和至少一个额外的端子，其电连接到附加的半导体芯片并与多个主端子中的至少一个接触。

公开(公告)号：US08653639B2

公开(公告)日：2014-02-18

申请号：US13156808

申请日：2011-06-09

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC: H01L21/02

CPC classification number: H01L21/561 ,  H01L21/6835 ,  H01L22/22 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/3511 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/82 ,  H01L2224/0231 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

Abstract: A layered chip package includes a main body and wiring. The main body has a main part. The main part has a top surface and a bottom surface and includes a plurality of layer portions that are stacked. The wiring includes a plurality of lines passing through all the plurality of layer portions. Each layer portion includes a semiconductor chip and a plurality of electrodes. The semiconductor chip has a first surface, and a second surface opposite thereto. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. The plurality of layer portions include two or more pairs of first and second layer portions in each of which the first and second layer portions are arranged so that the first or second surfaces of the respective semiconductor chips face each other. The plurality of electrodes include a plurality of first connection parts and a plurality of second connection parts. In the first layer portion, the plurality of first connection parts are in contact with the plurality of lines. In the second layer portion, the plurality of second connection parts are in contact with the plurality of lines.

Abstract translation: 分层芯片封装包括主体和布线。 主体有一个主要部分。 主要部分具有顶表面和底表面，并且包括堆叠的多个层部分。 布线包括穿过所有多个层部分的多条线。 各层部分包括半导体芯片和多个电极。 半导体芯片具有第一表面和与其相对的第二表面。 多个电极设置在半导体芯片的第一表面的一侧。 多个层部分包括两对或更多对第一和第二层部分，其中每个第一和第二层部分中的第一和第二层部分被布置成使得各个半导体芯片的第一或第二表面彼此面对。 多个电极包括多个第一连接部和多个第二连接部。 在第一层部分中，多个第一连接部分与多条线接触。 在第二层部分中，多个第二连接部分与多条线接触。

公开(公告)号：US08618646B2

公开(公告)日：2013-12-31

申请号：US12902600

申请日：2010-10-12

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC: H01L23/02

CPC classification number: H01L24/92 ,  H01L22/22 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03009 ,  H01L2224/0362 ,  H01L2224/037 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A layered chip package includes a main body. The main body includes a main part, and further includes first terminals and second terminals disposed on the top and bottom surfaces of the main part, respectively. The main part includes first and second layer portions, and through electrodes penetrating them. The through electrodes are electrically connected to the first and second terminals. Each of the layer portions includes a semiconductor chip having a first surface and a second surface opposite thereto, and further includes surface electrodes. The surface electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the surface electrodes of the first layer portion. The second terminals are formed by using the surface electrodes of the second layer portion.

Abstract translation: 分层芯片封装包括主体。 主体包括主要部分，并且还包括分别设置在主要部分的顶表面和底表面上的第一端子和第二端子。 主要部分包括第一和第二层部分，以及贯穿它们的电极。 通孔电连接到第一和第二端子。 每个层部分包括具有第一表面和与其相对的第二表面的半导体芯片，并且还包括表面电极。 表面电极设置在与第二表面相对的半导体芯片的一侧上。 第一和第二层部分彼此接合，使得相应的第二表面彼此面对。 第一端子通过使用第一层部分的表面电极形成。 第二端子通过使用第二层部分的表面电极形成。

公开(公告)号：US08587125B2

公开(公告)日：2013-11-19

申请号：US12869471

申请日：2010-08-26

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

IPC: H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00

CPC classification number: H01L21/76898 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/02 ,  H01L24/24 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L24/74 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/24011 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/32148 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2221/68304

Abstract: A layered chip package includes a main body, and wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of semiconductor chips stacked, and a plurality of electrodes that electrically connect the semiconductor chips to the wires. A method of manufacturing the layered chip package includes the steps of: fabricating a substructure that includes an array of a plurality of pre-separation main bodies and a plurality of holes for accommodating a plurality of preliminary wires, the holes being formed between two adjacent pre-separation main bodies; forming the preliminary wires in the plurality of holes by plating; and cutting the substructure so that the plurality of pre-separation main bodies are separated from each other and the preliminary wires are split into two sets of wires of two separate main bodies, whereby a plurality of layered chip packages are formed.

Abstract translation: 分层芯片封装包括主体和布置在主体的侧表面上的多根导线的布线。 主体包括堆叠的多个半导体芯片和将半导体芯片电连接到导线的多个电极。 制造层状芯片封装的方法包括以下步骤：制造包括多个预分离主体的阵列和用于容纳多条初级线的多个孔的子结构，所述孔形成在两个相邻的预制 分离主体; 通过电镀在多个孔中形成预备的电线; 并且切割所述子结构，使得所述多个预分离主体彼此分离，并且所述预备线被分成两组分离的主体的两组线，由此形成多个分层的芯片封装。

公开(公告)号：US08569878B2

公开(公告)日：2013-10-29

申请号：US12588659

申请日：2009-10-22

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

IPC: H01L23/52 ,  H01L23/48 ,  H01L21/60

CPC classification number: H01L25/0652 ,  H01L21/56 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/96 ,  H01L2221/68377 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13022 ,  H01L2224/16 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2225/06551 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00

Abstract: A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a device region in contact with at least any one of the plurality of groove portions and having a semiconductor device formed therein; a surface insulating layer formed to cover the device region and constituting a surface layer of the semiconductor substrate; and a wiring electrode connected to the semiconductor device and formed in a protruding shape rising above a surface of the surface insulating layer. The semiconductor substrate can be manufactured by forming a plurality of groove portions along scribe lines; applying an insulating material to a surface on a side where the plurality of groove portions are formed to form a surface insulating layer; and forming a wiring electrode connected to the semiconductor device and in a protruding shape rising above a surface of the surface insulating layer, after the formation of the surface insulating layer.

Abstract translation: 半导体基板具有沿划线形成的多个槽部。 半导体衬底包括：与多个沟槽部分中的至少一个接触并且具有形成在其中的半导体器件的器件区域; 形成为覆盖所述器件区域并构成所述半导体衬底的表面层的表面绝缘层; 以及连接到所述半导体器件并且形成为在所述表面绝缘层的表面上方上升的突出形状的布线电极。 可以通过沿划线形成多个槽部来制造半导体衬底; 将绝缘材料施加到形成所述多个槽部的一侧的表面上以形成表面绝缘层; 以及在形成所述表面绝缘层之后，形成连接到所述半导体器件并且以表面绝缘层的表面上方突出的形状的布线电极。

公开(公告)号：US20130279044A1

公开(公告)日：2013-10-24

申请号：US13450606

申请日：2012-04-19

Applicant: Wei XIONG ,  Panjalak Rokrakthong ,  Kenjiro Hata ,  Kazushi Nishiyama ,  Daisuke Iitsuka ,  Atsushi Iijima

Inventor： Wei XIONG ,  Panjalak Rokrakthong ,  Kenjiro Hata ,  Kazushi Nishiyama ,  Daisuke Iitsuka ,  Atsushi Iijima

IPC: H01L41/04 ,  G11B17/02 ,  G11B5/127 ,  H01L41/22

CPC classification number: H01L41/1876 ,  G11B5/483 ,  G11B5/5552 ,  H01L41/0805 ,  H01L41/316 ,  Y10T428/1179

Abstract: A thin film piezoelectric element of the present invention includes a substrate and a piezoelectric thin film stack formed on the substrate. The piezoelectric thin film stack includes a top electrode layer, a bottom electrode layer and a piezoelectric layer sandwiched between the top electrode layer and the bottom electrode layer, wherein the piezoelectric layer includes a first piezoelectric layer and a second piezoelectric layer whose compositions have different phase structures. The present invention can obtain high piezoelectric constants, enhanced coercive field strength, thereby enabling larger applied field strength without depolarization and achieving a large stroke for its applied device.

Abstract translation: 本发明的薄膜压电元件包括​​在基板上形成的基板和压电薄膜叠层体。 压电薄膜叠层包括顶电极层，底电极层和夹在顶电极层和底电极层之间的压电层，其中压电层包括第一压电层和第二压电层，其组成具有不同的相位 结构。 本发明可以获得高压电常数，增强的矫顽场强度，从而能够实现更大的施加场强而不去极化并且为其施加的装置实现大的冲程。

公开(公告)号：US08541887B2

公开(公告)日：2013-09-24

申请号：US12875710

申请日：2010-09-03

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC: H01L25/00

CPC classification number: H01L21/6835 ,  H01L21/563 ,  H01L23/3192 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2746 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32148 ,  H01L2224/81121 ,  H01L2224/8113 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82005 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83444 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2221/68304

Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. Each layer portion includes a semiconductor chip having a first surface and a second surface opposite thereto, and includes a plurality of electrodes. The electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the electrodes of the first layer portion, and the second terminals are formed by using the electrodes of the second layer portion.

Abstract translation: 分层芯片封装包括主体和布线，其包括布置在主体的侧表面上的多根导线。 主体包括：主要部分，包括第一和第二层部分; 以及多个第一和第二端子，其分别设置在主要部分的顶表面和底表面上，并且电连接到多个导线。 每个层部分包括具有第一表面和与其相对的第二表面的半导体芯片，并且包括多个电极。 电极设置在与第二表面相对的半导体芯片的一侧上。 第一和第二层部分彼此接合，使得相应的第二表面彼此面对。 通过使用第一层部分的电极形成第一端子，并且通过使用第二层部分的电极形成第二端子。

公开(公告)号：US08514520B2

公开(公告)日：2013-08-20

申请号：US13088852

申请日：2011-04-18

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Atsushi Iijima

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Atsushi Iijima

IPC: G11B5/11 ,  G11B5/147 ,  G11B5/187

CPC classification number: G11B5/1278 ,  G11B5/3146 ,  G11B5/3163 ,  G11B5/3967 ,  Y10T29/49032

Abstract: A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, and a thin-film coil are laminated on a substrate. The write shield layer has an opposing shield part opposing the main magnetic pole layer and a front shield part. The front shield part is connected to the opposing shield part without straddling the thin-film coil. Besides, the front shield part has a shield front end face disposed in the medium-opposing surface and a shield upper end face formed distanced from the medium-opposing surface. Further, the front shield part has a shield connecting part. The shield front end face is connected to the shield upper end face by the shield connecting part.

Abstract translation: 薄膜磁头被构造为使得主磁极层，写入屏蔽层，间隙层和薄膜线圈层叠在基板上。 写屏蔽层具有与主磁极层相对的相对的屏蔽部分和前屏蔽部分。 前屏蔽部分连接到相对的屏蔽部分而不跨越薄膜线圈。 此外，前屏蔽部分具有设置在介质相对表面中的屏蔽前端面和远离介质相对表面形成的屏蔽上端面。 此外，前屏蔽部具有屏蔽连接部。 屏蔽前端面通过屏蔽连接部与屏蔽上端面连接。

公开(公告)号：US20130176644A1

公开(公告)日：2013-07-11

申请号：US13344081

申请日：2012-01-05

Applicant: Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hironori ARAKI ,  Shigeki TANEMURA ,  Kazuki SATO ,  Atsushi IIJIMA

Inventor： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hironori ARAKI ,  Shigeki TANEMURA ,  Kazuki SATO ,  Atsushi IIJIMA

IPC: G11B5/17 ,  G11B5/127 ,  G11B5/48

CPC classification number: G11B5/1278 ,  G11B5/3116 ,  G11B5/3163 ,  Y10T29/49021

Abstract: A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, a thin-film coil and a shield magnetic layer are laminated on a substrate. The thin-film magnetic head has a shield magnetic layer. This thin-film magnetic head has a hard guard frame layer surrounding an equidistant coil part, disposed at a position equidistant from the substrate, from outside and being in direct contact with almost a whole outside surface defining an outer shape of the equidistant coil part.

Abstract translation: 薄膜磁头被构造成使得主磁极层，写入屏蔽层，间隙层，薄膜线圈和屏蔽磁性层被层压在基板上。 薄膜磁头具有屏蔽磁性层。 该薄膜磁头具有围绕等离子体线圈部分的等距线圈部分的硬保护框架层，其设置在距离基板等距离的位置，并且与限定等距线圈部分的外部形状的几乎整个外表面直接接触。

公开(公告)号：US08441755B2

公开(公告)日：2013-05-14

申请号：US13208980

申请日：2011-08-12

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Kazuki Sato ,  Atsushi Iijima

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Kazuki Sato ,  Atsushi Iijima

IPC: G11B5/17

CPC classification number: G11B5/17 ,  G11B5/1278 ,  G11B5/3116 ,  G11B5/3123 ,  G11B5/3146 ,  G11B5/315 ,  Y10T29/49021

Abstract: A magnetic head includes: a main pole; a coil; a first shield having an end face that is located in a medium facing surface at a position forward of an end face of the main pole along a direction of travel of a recording medium; and a first return path section disposed forward of the main pole along the direction of travel of the recording medium. The first return path section connects part of the main pole away from the medium facing surface to the first shield so that a first space is defined. The coil includes a first portion having a planar spiral shape and wound around a core part of the first return path section. The first portion includes first and second coil elements that each extend through the first space. No part of the coil other than the first and second coil elements exists in the first space.

Abstract translation: 磁头包括：主极; 线圈 第一屏蔽，其具有端面，所述端面沿着记录介质的行进方向位于所述主极端面的前端的位置处于介质相对表面; 以及第一返回路径部分，其沿着记录介质的行进方向设置在主极的前方。 第一返回路径部分将主极的远离介质面的表面连接到第一屏蔽，从而限定第一空间。 线圈包括具有平面螺旋形状并缠绕在第一返回路径部分的芯部分上的第一部分。 第一部分包括每个延伸穿过第一空间的第一和第二线圈元件。 除了第一和第二线圈元件之外，第一空间中不存在线圈的一部分。