公开(公告)号：US08852968B2

公开(公告)日：2014-10-07

申请号：US13768870

申请日：2013-02-15

Applicant: Liang Li ,  Zheng Zou ,  Huang Liu ,  Alex See

Inventor： Liang Li ,  Zheng Zou ,  Huang Liu ,  Alex See

IPC: H01L21/66

CPC classification number: H01L22/12 ,  G01B2210/56

Abstract: Methods of deducing oxide thickness using calculated and measured scattering spectra are provided. Embodiments include depositing an oxide over a semiconductor wafer, reducing the oxide from a portion of the semiconductor wafer, and deducing a thickness of oxide remaining at a location within the portion using scatterometric metrology. Embodiments further include deducing the thickness by: calculating scattering spectra for a plurality of oxide thicknesses, producing calculated scattering spectra, monitoring scattering spectra at the location within the portion of the semiconductor wafer, comparing the monitored scattering spectra at the location to the calculated scattering spectra, determining a closest matching calculated scattering spectra to the monitored scattering spectra at the location, and obtaining an oxide thickness corresponding to the closest matching calculated scattering spectra.

Abstract translation: 提供了使用计算和测量的散射光谱推导氧化物厚度的方法。 实施例包括在半导体晶片上沉积氧化物，从半导体晶片的一部分还原氧化物，并使用散射测量法推算残留在该部分内部的氧化物的厚度。 实施例还包括通过以下方式推导厚度：计算多个氧化物厚度的散射光谱，产生计算的散射光谱，监测半导体晶片部分内的位置处的散射光谱，将该位置处的所监视的散射光谱与计算出的散射光谱进行比较 确定与所述位置处的所监视的散射光谱最接近的匹配计算的散射光谱，以及获得对应于最接近的匹配计算的散射光谱的氧化物厚度。

公开(公告)号：US08569173B2

公开(公告)日：2013-10-29

申请号：US13314270

申请日：2011-12-08

Applicant: Liang Li ,  Huang Liu ,  Alex See ,  Soh Yun Siah ,  Xue Song Rao ,  Peng Zhou

Inventor： Liang Li ,  Huang Liu ,  Alex See ,  Soh Yun Siah ,  Xue Song Rao ,  Peng Zhou

IPC: H01L21/302

CPC classification number: H01L27/11534 ,  H01L21/28273

Abstract: Disclosed herein are various methods of protecting elevated polysilicon structures during etching processes. In one example, the method includes forming a layer stack above a semiconducting substrate for a memory device, forming a protective mask layer above the layer stack of the memory device and performing at least one etching process to define a gate electrode for a transistor while the protective mask is in position above the layer stack for the memory device.

Abstract translation: 本文公开了在蚀刻工艺期间保护升高的多晶硅结构的各种方法。 在一个示例中，该方法包括在用于存储器件的半导体衬底之上形成层堆叠，在存储器件的层堆叠之上形成保护掩模层，并执行至少一个蚀刻工艺以限定晶体管的栅电极，而 保护罩位于存储器件的层堆叠之上。

公开(公告)号：US07928020B2

公开(公告)日：2011-04-19

申请号：US11862865

申请日：2007-09-27

Applicant: Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. Alex See ,  Meisheng Zhou ,  Liang Choo Hsia

Inventor： Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. Alex See ,  Meisheng Zhou ,  Liang Choo Hsia

IPC: H01L21/00

CPC classification number: H01L21/3143 ,  H01L21/0214 ,  H01L21/02332 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/513 ,  H01L29/518

Abstract: A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon oxide layer by applying a nitrogen plasma. After applying nitrogen plasma, the silicon oxide layer is annealed. The processes of introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer are repeated to create a bi-modal nitrogen concentration profile in the silicon oxide layer. In the silicon oxide layer, the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is situated in proximity to the surface region. A method for fabricating a semiconductor device is incorporating the nitrogen-containing silicon oxide layers also disclosed.

Abstract translation: 一种含氮介电层的制造方法和包括在基板上形成氧化硅层的电介质层的半导体器件，使得界面区域与基板相邻，表面区域与界面区域相对。 通过施加氮等离子体将氮引入到氧化硅层中。 在施加氮等离子体之后，将氧化硅层退火。 重复将氧气引入氧化硅层并退火氧化硅层的过程，以在氧化硅层中产生双峰氮浓度分布。 在氧化硅层中，峰值氮浓度远离界面区域，并且峰值氮浓度中的至少一个位于表面区域附近。 还公开了一种制造半导体器件的方法，其中还包括含氮氧化硅层。

公开(公告)号：US07527900B2

公开(公告)日：2009-05-05

申请号：US11164127

申请日：2005-11-10

Applicant: Wen-Zhan Zhou ,  Jin Yu ,  Kai-Hung Alex See

Inventor： Wen-Zhan Zhou ,  Jin Yu ,  Kai-Hung Alex See

IPC: G03F1/00

CPC classification number: G03F1/36 ,  G03F1/32 ,  G03F1/62

Abstract: An OPC method includes providing a primary mask having a primary pattern, forming an assist mask having a correction pattern substantially complementary to the primary pattern, and forming a reticle by overlapping the primary mask and the assist mask. The light transmittance of the correction pattern is adjustable so as to equalize the light intensity distribution of the primary mask.

Abstract translation: OPC方法包括提供具有初级图案的初级掩模，形成具有与初级图案基本上互补的校正图案的辅助掩模，以及通过与初级掩模和辅助掩模重叠来形成掩模版。 校正图案的透光率可调，以平衡初级掩模的光强分布。

公开(公告)号：US20070066047A1

公开(公告)日：2007-03-22

申请号：US11162647

申请日：2005-09-18

Applicant: Jianhui Ye ,  Kai Hung Alex See ,  Tien-Cheng Lan ,  Meisheng Zhou

Inventor： Jianhui Ye ,  Kai Hung Alex See ,  Tien-Cheng Lan ,  Meisheng Zhou

IPC: H01L21/4763 ,  H01L21/302

CPC classification number: H01L21/31144 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an opening on a material layer is provided. First, a dielectric layer is formed on the material layer. Then, a metallic hard mask layer and a cap layer are sequentially formed on the dielectric layer. Thereafter, a patterned photoresist layer is formed on the cap layer. The patterned photoresist layer exposes a portion of the surface of the cap layer. After that, a first etching operation is carried out using the patterned photoresist layer as a mask to remove a portion of the cap layer and the metallic hard mask layer until the surface of the dielectric layer is exposed. Then, the photoresist layer is removed. A second etching operation is carried out using the cap layer and the metallic hard mask layer as a mask to remove a portion of the dielectric layer and form an opening.

Abstract translation: 提供了在材料层上形成开口的方法。 首先，在材料层上形成电介质层。 然后，在电介质层上依次形成金属硬掩模层和盖层。 此后，在盖层上形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层暴露盖层表面的一部分。 之后，使用图案化的光致抗蚀剂层作为掩模进行第一蚀刻操作，以除去覆盖层和金属硬掩模层的一部分，直到暴露介电层的表面。 然后，除去光致抗蚀剂层。 使用盖层和金属硬掩模层作为掩模进行第二蚀刻操作，以去除电介质层的一部分并形成开口。

公开(公告)号：US07112499B2

公开(公告)日：2006-09-26

申请号：US10759671

申请日：2004-01-16

Applicant: Chyiu Hyia Poon ,  Leng Seow Tan ,  Byung Jin Cho ,  Alex See ,  Mousumi Bhat

Inventor： Chyiu Hyia Poon ,  Leng Seow Tan ,  Byung Jin Cho ,  Alex See ,  Mousumi Bhat

IPC: H01L21/336 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L21/268 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823418

Abstract: A process is described to form a semiconductor device such as MOSFET or CMOS with shallow junctions in the source/drain extension regions. After forming the shallow trench isolations and the gate stack, sidewall dielectric spacers are removed. A pre-amorphizing implant (PAI) is performed with Ge+ or Si+ ions to form a thin PAI layer on the surface of the silicon regions adjacent to the gate stack. B+ ion implantation is then performed to form source/drain extension (SDE) regions. The B+ implant step is then followed by multiple-pulsed 248 nm KrF excimer laser anneal with pulse duration of 23 ns. This step is to reduce the sheet resistance of the junction through the activation of the boron dopant in the SDE junctions. Laser anneal is then followed by rapid thermal anneal (RTA) to repair the residual damage and also to induce out-diffusion of the boron to yield shallower junctions than the just-implanted junctions prior to RTA.

Abstract translation: 描述了一种工艺以在源极/漏极延伸区域中形成具有浅结的诸如MOSFET或CMOS的半导体器件。 在形成浅沟槽隔离物和栅极堆叠之后，去除侧壁电介质间隔物。 用Ge + +或Si + +离子进行预非晶化植入物（PAI），以在邻近栅叠层的硅区域的表面上形成薄的PAI层。 然后进行离子注入以形成源极/漏极延伸（SDE）区域。 然后，B + / /> /注入步骤之后是脉冲持续时间为23ns的多脉冲248nm KrF准分子激光退火。 该步骤是通过SDE结中的硼掺杂剂的激活来降低结的薄层电阻。 然后激光退火之后是快速热退火（RTA）以修复残余损伤，并且还引起硼的扩散，从而产生比RTA之前刚刚植入的结更浅的结。

公开(公告)号：US07094669B2

公开(公告)日：2006-08-22

申请号：US10910499

申请日：2004-08-03

Applicant: Xiaomei Bu ,  Alex See ,  Tae Jong Lee ,  Fan Zhang ,  Yeon Kheng Lim ,  Liang Choo Hsia

Inventor： Xiaomei Bu ,  Alex See ,  Tae Jong Lee ,  Fan Zhang ,  Yeon Kheng Lim ,  Liang Choo Hsia

IPC: H01L21/46 ,  H01L21/78 ,  H01L21/301 ,  H01L21/76 ,  H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.

公开(公告)号：US07091092B2

公开(公告)日：2006-08-15

申请号：US10062227

申请日：2002-02-05

Applicant: Sneedharan Pillai Sneelal ,  Francis Poh ,  James Lee ,  Alex See ,  C. K. Lau ,  Ganesh Shankar Samudra

Inventor： Sneedharan Pillai Sneelal ,  Francis Poh ,  James Lee ,  Alex See ,  C. K. Lau ,  Ganesh Shankar Samudra

IPC: H01L21/336

CPC classification number: H01L29/66621 ,  H01L29/66545 ,  H01L29/7834

Abstract: A method for forming a self-aligned, recessed channel, MOSFET device that alleviates problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is described. A thin pad oxide layer is grown overlying the substrate and a gate recess, followed by deposition of a thick silicon nitride layer filling the gate recess. The top surface is planarized exposing the pad oxide layer. An additional oxide layer is grown, thickening the pad oxide layer. A portion of the silicon nitride layer is etched away and additional oxide layer is again grown. This forms a tapered oxide layer along the sidewalls of the gate recess. The remaining silicon nitride layer is removed. The oxide layer at the bottom of the gate recess is removed and a gate dielectric layer is grown. Gate polysilicon is deposited filling the gate recess. S/D implantations, metallization, and passivation complete fabrication of the device.

Abstract translation: 描述了一种用于形成自对准凹槽的MOSFET器件的方法，该MOSFET器件在减少电极间电容的同时减轻由短沟道和热载流子效应导致的问题。 生长覆盖衬底和栅极凹槽的薄衬垫氧化物层，随后沉积填充栅极凹槽的厚氮化硅层。 平坦化顶表面暴露氧化垫层。 生长另外的氧化物层，使衬垫氧化物层变厚。 蚀刻掉氮化硅层的一部分，再次生长另外的氧化物层。 这沿着栅极凹槽的侧壁形成锥形氧化物层。 剩余的氮化硅层被去除。 除去栅极凹部底部的氧化物层，生长栅极电介质层。 栅极多晶硅沉积填充栅极凹槽。 S / D注入，金属化和钝化完整的器件制造。

公开(公告)号：US07030451B2

公开(公告)日：2006-04-18

申请号：US11081908

申请日：2005-03-15

Applicant: Pooi See Lee ,  Kin Leong Pey ,  Alex See ,  Lap Chan

Inventor： Pooi See Lee ,  Kin Leong Pey ,  Alex See ,  Lap Chan

IPC: H01L29/78

CPC classification number: H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/4933

Abstract: A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

公开(公告)号：US06905964B2

公开(公告)日：2005-06-14

申请号：US10339185

申请日：2003-01-09

Applicant: Boon Kiat Lim ,  Alex See

Inventor： Boon Kiat Lim ,  Alex See

IPC: H01L21/285 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76849 ,  H01L21/28562

Abstract: An improved and new process for fabricating self-aligned metal barriers by atomic layer deposition, ALD, capable of producing extremely thin, uniform, and conformal metal barrier films, selectively depositing on copper, not on silicon dioxide interlevel dielectric, in multi-layer dual damascene trench/via processing. Silicon nitride is presently used as a insulating copper barrier. However, silicon nitride has a relatively high dielectric constraint, which deteriorates ICs with increased RC delay. Copper metal barriers of niobium and tantalum have been deposited by atomic layer deposition on copper. With high deposition selectivity, the barrier metal is only deposited over copper, not on silicon dioxide, which eliminates the need of an insulating barrier of silicon nitride.

Abstract translation: 一种通过原子层沉积制造自对准金属屏障的改进和新工艺，ALD能够生产极薄，均匀和保形的金属阻挡膜，选择性地沉积在铜上，而不是在二氧化硅层间电介质上沉积在多层双层 大马士革沟/通孔加工。 氮化硅目前被用作绝缘铜屏障。 然而，氮化硅具有相对较高的介电约束，其使具有增加的RC延迟的IC劣化。 铌和钽的铜金属屏障已经通过原子层沉积沉积在铜上。 具有高的沉积选择性，阻挡金属仅沉积在铜上，而不是在二氧化硅上沉积，这消除了氮化硅的绝缘势垒的需要。