公开(公告)号：US11342449B2

公开(公告)日：2022-05-24

申请号：US17095230

申请日：2020-11-11

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Jean Jimenez Martinez

IPC分类号： H01L29/808 ,  H01L29/66 ,  H01L21/8248 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L27/112

摘要： An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.

公开(公告)号：US10720453B2

公开(公告)日：2020-07-21

申请号：US16394472

申请日：2019-04-25

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Bahman Hekmatshoartabari

IPC分类号： H01L29/66 ,  H01L27/12 ,  H03K17/567 ,  H03K17/70 ,  H01L21/285 ,  H01L29/40 ,  H01L29/45 ,  H01L23/522 ,  H01L23/532 ,  H01L21/84 ,  H01L29/808 ,  H01L29/04 ,  H01L29/08 ,  H01L29/16 ,  H01L29/735 ,  G06N3/04 ,  H01L27/06 ,  H01L29/417 ,  H01L21/8248 ,  H01L29/10 ,  G06N3/063 ,  H01L21/3213 ,  H01L29/737 ,  H01L29/80

摘要： A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.

公开(公告)号：US09337185B2

公开(公告)日：2016-05-10

申请号：US14561357

申请日：2014-12-05

申请人： Infineon Technologies AG

发明人： Frank Pfirsch ,  Dorothea Werber ,  Carsten Schaeffer

IPC分类号： H01L21/70 ,  H01L21/8248 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/47 ,  H01L29/739 ,  H01L29/66 ,  H01L27/07

CPC分类号： H01L27/0635 ,  H01L27/0727 ,  H01L29/0615 ,  H01L29/0804 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/47 ,  H01L29/66348 ,  H01L29/7397

摘要： A semiconductor device includes a first doping region extending from a main surface of a semiconductor substrate into the semiconductor substrate. Further, the semiconductor device includes a second doping region arranged adjacent to the first doping region. The first doping region includes at least one low doping dose portion extending from the main surface of the semiconductor substrate to the second doping region. A doping dose within the low doping dose portion of the first doping region is less than 3 times a breakdown charge. Additionally, the semiconductor device includes a first electrode structure in contact with the first doping region at the main surface of the semiconductor substrate. The work function of the first electrode structure at the main surface of the semiconductor substrate is larger than 4.9 eV or lower than 4.4 eV.

摘要翻译： 半导体器件包括从半导体衬底的主表面延伸到半导体衬底中的第一掺杂区域。 此外，半导体器件包括邻近第一掺杂区布置的第二掺杂区。 第一掺杂区域包括从半导体衬底的主表面延伸到第二掺杂区域的至少一个低掺杂剂量部分。 第一掺杂区域的低掺杂剂量部分内的掺杂剂量小于击穿电荷的3倍。 另外，半导体器件包括与半导体衬底的主表面处的第一掺杂区域接触的第一电极结构。 第一电极结构在半导体衬底的主表面上的功函数大于4.9eV或低于4.4eV。

公开(公告)号：US08563986B2

公开(公告)日：2013-10-22

申请号：US12611165

申请日：2009-11-03

申请人： Qingchun Zhang

发明人： Qingchun Zhang

IPC分类号： H01L27/06 ,  H01L29/24 ,  H01L21/8248

CPC分类号： H01L29/7802 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395

摘要： Semiconductor switching devices include a wide band-gap drift layer having a first conductivity type (e.g., n-type), and first and second wide band-gap well regions having a second conductivity type (e.g., p-type) on the wide band-gap drift layer. First and second wide band-gap source/drain regions of the first conductivity type are on the first and second wide band-gap well regions, respectively. A wide band-gap JFET region having the first conductivity type is provided between the first and second well regions. This JFET region includes a first local JFET region that is adjacent a side surface of the first well region and a second local JFET region that is adjacent a side surface of the second well region. The local JFET regions have doping concentrations that exceed a doping concentration of a central portion of the JFET region that is between the first and second local JFET regions of the JFET region.

摘要翻译： 半导体开关器件包括具有第一导电类型（例如，n型）的宽带隙漂移层和在宽带上具有第二导电类型（例如p型）的第一和第二宽带隙阱区 漂移层。 第一和第二宽带隙源极/漏极区分别位于第一和第二宽带隙阱区上。 具有第一导电类型的宽带隙JFET区域设置在第一和第二阱区之间。 该JFET区域包括与第一阱区域的侧表面相邻的第一局部JFET区域和与第二阱区域的侧表面相邻的第二局部JFET区域。 局部JFET区域具有超过JFET区域的第一和第二局部JFET区域之间的JFET区域的中心部分的掺杂浓度的掺杂浓度。

公开(公告)号：US20120235731A1

公开(公告)日：2012-09-20

申请号：US13427488

申请日：2012-03-22

申请人： Bin Li ,  Peter J. Zampardi, JR. ,  Andre G. Metzger

发明人： Bin Li ,  Peter J. Zampardi, JR. ,  Andre G. Metzger

IPC分类号： G05F3/02 ,  H01L21/8248 ,  H01Q23/00 ,  H01L29/93

CPC分类号： H01L27/0635 ,  H01L21/8249 ,  H01L27/0605 ,  H01L27/0623 ,  H01L27/0808 ,  H01L27/0811 ,  H01L29/1095 ,  H01L29/93 ,  H01L29/94 ,  H03J3/185

摘要： A varactor includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET shares an electrical connection with a base of the BJT, and in which a reverse voltage applied to the back gate of the FET creates a continuously variable capacitance in a channel of the FET.

摘要翻译： 变容二极管包括与双极结型晶体管（BJT）的至少一部分集成的场效应晶体管（FET），其中FET的背栅与BJT的基极共享电连接，并且其中反向电压 施加到FET的背栅极在FET的沟道中产生连续可变的电容。

公开(公告)号：US20090114950A1

公开(公告)日：2009-05-07

申请号：US11597533

申请日：2005-05-19

申请人： Prabhat Agarwal ,  Jan Willem Slotboom ,  Gerben Doornbos

发明人： Prabhat Agarwal ,  Jan Willem Slotboom ,  Gerben Doornbos

IPC分类号： H01L21/336 ,  H01L21/8249 ,  H01L21/8232 ,  H01L29/78 ,  H01L29/80 ,  H01L21/8234 ,  H01L21/8248

CPC分类号： H01L21/8249

摘要： The invention relates to a semiconductor device (10) comprising a substrate (11) and a semiconductor body (1) of silicon having a semiconductor layer structure comprising, in succession, a first and a second semiconductor layer (2, 3), and having a surface region of a first conductivity type which is provided with a field effect transistor (M) with a channel of a second conductivity type, opposite to the first conductivity type, wherein the surface region is provided with source and drain regions (4A, 4B) of the second conductivity type for the field effect transistor (M) and with—interposed between said source and drain regions—a channel region (3A) with a lower doping concentration which forms part of the second semiconductor layer (3) and with a buried first-conductivity-type semiconductor region (2A), buried below the channel region (3A), with a doping concentration that is much higher than that of the channel region (3A) and which forms part of the first semiconductor layer (2). According to the invention, the semiconductor body (1) is provided not only with the field effect transistor (M) but also with a bipolar transistor (B) with emitter, base and collector regions (5A, 5B, 5C) of respectively the second, the first and the second conductivity type, and the emitter region (5A) is formed in the second semiconductor layer (3) and the base region (5B) is formed in the first semiconductor layer (2). In this way a Bi(C)MOS IC (10) is obtained which is very suitable for high-frequency applications and which is easy to manufacture using a method according to the invention. Preferably the first semiconductor layer (2) comprises Si—Ge and is delta-doped, whereas the second semiconductor layer (3) comprises strained Si.

摘要翻译： 本发明涉及一种半导体器件（10），它包括具有半导体层结构的硅衬底（12）和半导体本体（1），半导体层结构依次包括第一和第二半导体层（2,3），并且具有 具有与第一导电类型相反的具有第二导电类型的沟道的场效应晶体管（M）的第一导电类型的表面区域，其中所述表面区域设置有源极和漏极区域（4A，4B） ）和用于场效应晶体管（M）的第二导电类型，并且插入在所述源极和漏极区之间 - 具有较低掺杂浓度的沟道区（3A），其形成第二半导体层（3）的一部分，并且具有 埋入第一导电型半导体区域（2A），其掺杂在沟道区域（3A）的下方，掺杂浓度比沟道区域（3A）的掺杂浓度高得多，并且形成第一半导体层（2）的一部分， 。 根据本发明，半导体本体（1）不仅设置有场效应晶体管（M），而且还具有双极晶体管（B），发射极，基极和集电极区域（5A，5B，5C）分别为第二 第一和第二导电类型和发射极区域（5A）形成在第二半导体层（3）中，并且基极区域（5B）形成在第一半导体层（2）中。 以这种方式获得了非常适合于高频应用并且易于使用根据本发明的方法制造的Bi（C）MOS IC（10）。 优选地，第一半导体层（2）包括Si-Ge并且是δ掺杂的，而第二半导体层（3）包括应变Si。

公开(公告)号：US20080230806A1

公开(公告)日：2008-09-25

申请号：US12069044

申请日：2008-02-07

申请人： Noren Pan ,  Andree Wibowo

发明人： Noren Pan ,  Andree Wibowo

IPC分类号： H01L27/06 ,  H01L21/8248

CPC分类号： H01L27/0605 ,  H01L21/8249 ,  H01L21/8252 ,  H01L27/0623

摘要： Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BIFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.

摘要翻译： 公开了使用两个单独的生长方法制造集成BiFET的方法和系统。 该方法的性能在第一制造环境中制造BIFET的FET部分。 该方法的性能在第二制造环境中制造BiFET的HBT部分。 通过在两个或更多个单独的反应器中分离FET部分和HBT部分的制造，可以实现两种器件的最佳器件性能。

公开(公告)号：US20080142854A1

公开(公告)日：2008-06-19

申请号：US11611222

申请日：2006-12-15

申请人： Harald Streif

发明人： Harald Streif

IPC分类号： H01L29/76 ,  H01L21/8248 ,  G05F1/10

CPC分类号： G11C11/4085

摘要： An electrical circuit comprising a first metal oxide silicon (MOS) n type field effect transistor (NFET) or p type field effect transistor (PFET) and a second MOS NFET or PFET of the same conductivity type as the first NFET or PFET, wherein the drain of the first NFET or PFET is directly connected to the source of the second NFET or PFET, and wherein the gate of the second NFET or PFET is at a voltage value which is equal to or lower than the drain voltage value of the second NFET or PFET in the case of an NFET and equal to or higher than the drain voltage value of the second NFET or PFET in the case of a PFET.

摘要翻译： 一种包括第一金属氧化物硅（MOS）n型场效应晶体管（NFET）或p型场效应晶体管（PFET）以及与第一NFET或PFET相同导电类型的第二MOS NFET或PFET的电路，其中， 第一NFET或PFET的漏极直接连接到第二NFET或PFET的源极，并且其中第二NFET或PFET的栅极处于等于或低于第二NFET或PFET的漏极电压值的电压值 或者在NFET的情况下为PFET，并且在PFET的情况下等于或高于第二NFET或PFET的漏极电压值。

公开(公告)号：US07195965B2

公开(公告)日：2007-03-27

申请号：US10302256

申请日：2002-11-22

申请人： John Lin ,  Philip L. Hower ,  Taylor R. Efland ,  Sameer Pendharkar ,  Vladimir Bolkhovsky

发明人： John Lin ,  Philip L. Hower ,  Taylor R. Efland ,  Sameer Pendharkar ,  Vladimir Bolkhovsky

IPC分类号： H01L21/8248

CPC分类号： H01L29/7816 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66674 ,  H01L29/7322 ,  H01L29/8611

摘要： The concept of the present invention describes a semiconductor device with a junction 504 between a lightly doped region 501 and a heavily doped region 502, wherein the junction has an elongated portion 504a and curved portions 504b. The doping concentration of the lightly doped region is configured so that it exhibits higher resistivity in the proximity 510 of the curved portion by an amount suitable to lower the electric field strength during device operation and thus to offset the increased field strength caused by the curved portion. As a consequence, the device breakdown voltage in the curved junction portion becomes equal to or greater than the breakdown voltage in the linear portion.

摘要翻译： 本发明的概念描述了在轻掺杂区域501和重掺杂区域502之间具有结504的半导体器件，其中该接合部具有细长部分504a和弯曲部分504b。 轻掺杂区域的掺杂浓度被配置为使得其在弯曲部分的接近510处表现出较高的电阻率，其量适于在器件操作期间降低电场强度，并因此抵消由弯曲部分引起的增加的场强 。 结果，弯曲接合部中的器件击穿电压变得等于或大于直线部分中的击穿电压。

公开(公告)号：US20050272207A1

公开(公告)日：2005-12-08

申请号：US11204215

申请日：2005-08-15

申请人： Richard Williams ,  Michael Cornell ,  Wai Chan

发明人： Richard Williams ,  Michael Cornell ,  Wai Chan

IPC分类号： H01L21/331 ,  H01L21/76 ,  H01L21/8222 ,  H01L21/8224 ,  H01L21/8228 ,  H01L21/8234 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L27/088 ,  H01L29/73 ,  H01L29/732 ,  H01L21/336

CPC分类号： H01L27/0826 ,  H01L21/8224 ,  H01L21/82285 ,  H01L27/0821 ,  H01L29/6625 ,  H01L29/66272 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa. When the substrate is subjected to thermal processing, the buried layer diffuses upward, the dopant in the mesa diffuses downward until the two dopants merge to form an isolation region or a sinker extending downward from the surface of the epitaxial layer to the buried layer. In another embodiment, dopant is implanted between dielectrically filled trenches at a high energy up to several MeV, then diffused, combining the benefits of deep implantation and trenched constrained diffusion to achive deep diffusions with a minimal thermal budget.