公开(公告)号：US11469330B2

公开(公告)日：2022-10-11

申请号：US16888904

申请日：2020-06-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshinobu Asami

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/465 ,  H01L21/3115 ,  H01L21/469 ,  H01L27/12

Abstract: A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second oxide insulator, a gate insulating layer, a gate electrode layer, source and drain electrode layers and an insulating layer. The oxide semiconductor includes first to fifth regions. The first region overlaps with the source electrode layer. The second region overlaps with the drain electrode layer. The third region overlaps with the gate electrode layer. The fourth region is between the first region and the third region. The fifth region is between the second region and the third region. The fourth region and the fifth region each contain an element N (N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon). A top surface of the insulating layer is positioned at a lower level than top surfaces of the source and drain electrode layers.

公开(公告)号：US11257745B2

公开(公告)日：2022-02-22

申请号：US16641219

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Veronica Strong ,  Kristof Darmawikarta ,  Arnab Sarkar

IPC: H05K1/00 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  H05K1/18 ,  H05K3/02 ,  H05K3/10 ,  H05K3/40 ,  H05K3/46 ,  H01L21/00 ,  H01L21/02 ,  H01L21/31 ,  H01L21/44 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/70 ,  H01L21/469 ,  H01L21/4763 ,  H01L21/8246 ,  H01L23/00 ,  H01L23/28 ,  H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L23/58 ,  H01L23/485 ,  H01L23/495 ,  H01L23/498 ,  H01L23/522 ,  G06K19/02 ,  G06K19/077 ,  H05K3/18

Abstract: A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.

公开(公告)号：US10968517B2

公开(公告)日：2021-04-06

申请号：US16195463

申请日：2018-11-19

Applicant: KOKUSAI ELECTRIC CORPORATION

Inventor： Shin Sone ,  Masaya Nagato ,  Kenji Kameda ,  Kotaro Konno

IPC: H01L21/31 ,  H01L21/469 ,  C23C16/56 ,  C23C16/40 ,  C23C16/455 ,  H01L21/02 ,  C23C16/44

Abstract: There is provided a cleaning technique that includes supplying a hydrogen fluoride gas into a process vessel, in which a process of forming an oxide film containing at least one of carbon and nitrogen on a substrate has been performed, to remove a deposit containing at least one of carbon and nitrogen adhered to an interior of the process vessel, wherein the act of supplying the hydrogen fluoride gas is performed under a condition in which an etching rate of the deposit adhered to the interior of the process vessel is higher than an etching rate of a quartz member in the process vessel.

公开(公告)号：US10573498B2

公开(公告)日：2020-02-25

申请号：US15402142

申请日：2017-01-09

Applicant: APPLIED MATERIALS, INC.

Inventor： Bharath Swaminathan ,  Hanbing Wu ,  John Mazzocco

IPC: H01L21/31 ,  H01L21/469 ,  H01J37/32 ,  H01L21/687 ,  C23C14/34 ,  C23C14/50 ,  H01J37/34

Abstract: Embodiments of a method and apparatus for annealing a substrate are disclosed herein. In some embodiments, a substrate support includes a substrate support pedestal having an upper surface to support a substrate and an opposing bottom surface, wherein the substrate support pedestal is formed of a material that is transparent to radiation; a lamp assembly disposed below the substrate support pedestal and having a plurality of lamps configured to heat the substrate; a pedestal support extending through the lamp assembly to support the substrate support pedestal in a spaced apart relation to the plurality of lamps; a shaft coupled to a second end of the pedestal support opposite the first end; and a rotation assembly coupled to the shaft opposite the pedestal support to rotate the shaft, the pedestal support, and the substrate support pedestal with respect to the lamp assembly.

公开(公告)号：US10551741B2

公开(公告)日：2020-02-04

申请号：US16094119

申请日：2017-04-07

Applicant: ASM IP HOLDING B.V. ,  IMEC VZW

Inventor： Werner Knaepen ,  Jan Willem Maes ,  Maarten Stokhof ,  Roel Gronheid ,  Hari Pathangi Sriraman

IPC: G03F7/16 ,  H01L21/027 ,  H01L21/67 ,  H01L21/768 ,  H01L51/00 ,  H01L21/469 ,  H01L21/31 ,  B05D3/04 ,  B05D3/02

Abstract: A method of forming a directed self-assembled (DSA) layer on a substrate by: providing a substrate; applying a layer comprising a self-assembly material on the substrate; and annealing of the self-assembly material of the layer to form a directed self-assembled layer by providing a controlled temperature and gas environment around the substrate. The controlled gas environment comprises molecules comprising an oxygen element with a partial pressure between 10-2000 Pa.

公开(公告)号：US10354923B2

公开(公告)日：2019-07-16

申请号：US15610266

申请日：2017-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chun Huang ,  Bang-Tai Tang ,  Chih-Tang Peng ,  Tai-Chun Huang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L27/088 ,  H01L21/31 ,  H01L21/469

Abstract: A method includes performing an atomic layer deposition (ALD) process to deposit a dielectric material over a substrate, curing the deposited dielectric material using an ultra violet (UV) light, and annealing the deposited dielectric material after the curing.

公开(公告)号：US10211050B2

公开(公告)日：2019-02-19

申请号：US15237840

申请日：2016-08-16

Applicant: TOKYO ELECTRON LIMITED

Inventor： Hidetami Yaegashi ,  Kenichi Oyama ,  Masatoshi Yamato ,  Tomohiro Iseki ,  Toyohisa Tsuruda

IPC: G03F7/20 ,  G03F7/36 ,  G03F7/004 ,  H01L21/027 ,  H01L21/31 ,  H01L21/469

Abstract: There is provided a semiconductor device manufacturing method, including: a film forming process in which, by supplying a solution for modifying a surface layer of a resist to a target object having a resist pattern and allowing the solution to infiltrate into the resist, a film having elasticity and having no compatibility with the resist is formed in the surface layer of the resist; and a heating process in which the target object having the film formed thereon is heated.

公开(公告)号：US10192904B2

公开(公告)日：2019-01-29

申请号：US14432048

申请日：2014-07-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiang Liu

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/441 ,  H01L21/469 ,  H01L21/4757 ,  H01L21/4763 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786 ,  H01L21/28 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/49

Abstract: A manufacturing method of an array substrate, including: forming a pattern layer including a pixel electrode, and a pattern layer including a gate electrode and a gate line on a base substrate; on the substrate with the pattern layer including the gate electrode and the gate line formed thereon, forming a gate insulating layer, a pattern layer at least including a metal oxide semiconductor active layer and a pattern layer at least including an etch stop layer; wherein, a first via hole for exposing the pixel electrode is formed over the pixel electrode; on the substrate with the etch stop layer formed thereon, forming a pattern layer including a source electrode, a drain electrode and a data line; wherein, the source electrode and the drain electrode each contact a metal oxide semiconductor active layer, and the drain electrode is electrically connected to the pixel electrode through the first via hole.

公开(公告)号：US10128274B2

公开(公告)日：2018-11-13

申请号：US15434374

申请日：2017-02-16

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jae Woo Jeong

IPC: H01L27/12 ,  H01L21/311 ,  H01L21/32 ,  H01L21/469 ,  H01L29/49 ,  H01L21/308 ,  H01L27/32 ,  H01L21/3205

Abstract: A thin film transistor array panel including: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode overlapping the semiconductor layer, and a gate electrode overlapping the semiconductor layer; and a first ohmic contact disposed between the semiconductor layer and the source electrode and a second ohmic contact disposed between the semiconductor layer and the drain electrode. The semiconductor layer includes a channel part that does not overlap the source electrode and the drain electrode. The first ohmic contact includes a first edge and the second ohmic contact includes a second edge. The first and second edges face each other across the channel part of the semiconductor layer. The first edge of the first ohmic contact is protruded from the source electrode toward the channel part and the second edge of the second ohmic contact is protruded from the drain electrode toward the channel part.

公开(公告)号：US09966251B2

公开(公告)日：2018-05-08

申请号：US14681065

申请日：2015-04-07

Applicant: Hitachi Kokusai Electric Inc.

Inventor： Ryota Sasajima ,  Yoshiro Hirose ,  Yosuke Ota ,  Naonori Akae ,  Kojiro Yokozawa

IPC: H01L21/31 ,  H01L21/469 ,  H01L21/02 ,  C23C16/54 ,  C23C16/40 ,  C23C16/455 ,  C23C16/56 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/321

CPC classification number: H01L21/0223 ,  C23C16/402 ,  C23C16/45546 ,  C23C16/54 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02238 ,  H01L21/02244 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/31645 ,  H01L21/32051 ,  H01L21/321

Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: (a) forming an oxide film having a predetermined thickness on a substrate by alternately repeating: (a-1) forming a layer containing a predetermined element on the substrate by supplying a source gas containing the predetermined element into a process vessel accommodating the substrate and exhausting the source gas from the process vessel; and (a-2) changing the layer containing the predetermined element into an oxide layer by supplying an oxygen-containing gas and an hydrogen-containing gas into the process vessel, wherein inside of the process vessel is under a heated atmosphere having a pressure lower than an atmospheric pressure; and exhausting the oxygen-containing gas and the hydrogen-containing gas from the process vessel; and (b) modifying the oxide film formed on the substrate by supplying the oxygen-containing gas and the hydrogen-containing gas into the process vessel, wherein the inside of the process vessel is under the heated atmosphere having the pressure lower than the atmospheric pressure, and exhausting the oxygen-containing gas and the hydrogen-containing gas from the process vessel.