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    Position-limiting structure for backlight module, backlight module and display device
    4.
    发明授权
    Position-limiting structure for backlight module, backlight module and display device 有权

    公开(公告)号：US10018772B2

    公开(公告)日：2018-07-10

    申请号：US15108008

    申请日：2016-01-05

    Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI BOE DISPLAY LIGHT CO., LTD.

    Inventor： Xiang Liu

    IPC: F21V7/04 ,  F21V8/00

    CPC classification number: G02B6/0088

    Abstract: The invention provides a position-limiting structure for a backlight module, a backlight module and a display device, belongs to the field of display technology, and can solve the problem in the prior art that an alignment error occurs in the light-guiding plate due to the fact that the double-sided adhesive tape is adhered to fix the backplane and the light-guiding plate. The position-limiting structure for a backlight module of the invention is made of an elastic material, and is configured to be connected to the backplane; the position-limiting structure includes the position-limiting part, which is arranged outside an edge at least one non light-incoming side of the light-guiding plate and is configured to fix the light-guiding plate to the backplane.

    THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY DEVICE
    5.
    发明申请
    THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY DEVICE 审中-公开
    薄膜晶体管，制造薄膜晶体管的方法，阵列基板和显示器件

    公开(公告)号：US20160343739A1

    公开(公告)日：2016-11-24

    申请号：US15094553

    申请日：2016-04-08

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Xiang Liu

    IPC: H01L27/12 ,  H01L33/42 ,  H01L29/66 ,  H01L29/45 ,  H01L29/786

    CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66969 ,  H01L29/7869

    Abstract: Embodiments of the present invention disclose a thin film transistor, a method of manufacturing a thin film transistor, an array substrate and a display device, which may ensure electrical connection between source and drain electrodes and an active layer without configuring any through hole due to providing an etch stop layer between the active layer and the source and drain electrodes, a portion of the etch stop layer being in contact with the source and drain electrode is made of metal or metal alloy; and may ensure insulation between the source and the drain electrodes when the thin film transistor is turned-off, ensuring normal operation of the thin film transistor, by oxidating the portion of the etch stop layer at the position between the source and the drain electrodes as an insulating material. The etch stop layer may not only prevent the active layer from being damaged when etching the source and drain electrodes, but also prevent the active layer from other adverse effects from subsequent processes, such as adverse effects from water, hydrogen and oxygen, etc., thereby enhancing performance of the thin film transistor, just because of providing the etch stop layer between the active layer and the source and drain electrodes in the thin film transistor.

    Abstract translation: 本发明的实施例公开了薄膜晶体管，制造薄膜晶体管的方法，阵列基板和显示装置，其可以确保源极和漏极之间的电连接以及有源层，而不会由于提供任何通孔而构成任何通孔 在有源层和源极和漏极之间的蚀刻停止层，与源极和漏极接触的蚀刻停止层的一部分由金属或金属合金制成; 并且可以确保当薄膜晶体管截止时源极和漏极之间的绝缘，通过在源极和漏极之间的位置处氧化蚀刻停止层的部分来确保薄膜晶体管的正常操作，从而 绝缘材料。 蚀刻停止层不仅可以防止当蚀刻源极和漏极时活性层受损，而且可以防止活性层受到后续过程的其它不利影响，例如水，氢和氧等的不利影响， 从而提高薄膜晶体管的性能，只是因为在有源层和薄膜晶体管中的源极和漏极之间提供蚀刻停止层。

    Thin film transistor and method for manufacturing the same, array substrate and display device
    6.
    发明授权
    Thin film transistor and method for manufacturing the same, array substrate and display device 有权
    薄膜晶体管及其制造方法，阵列基板及显示装置

    公开(公告)号：US09240485B2

    公开(公告)日：2016-01-19

    申请号：US14352182

    申请日：2013-07-02

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Xiang Liu ,  Gang Wang ,  Jianshe Xue

    IPC: H01L29/786 ,  H01L29/45 ,  H01L21/441 ,  H01L27/12 ,  H01L29/49 ,  H01L29/66

    CPC classification number: H01L29/78606 ,  H01L21/441 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693

    Abstract: A thin film transistor comprises a substrate; a gate electrode, a source electrode, a drain electrode and a semiconductor layer formed on the substrate; a gate insulating layer between the gate electrode and the semiconductor layer or between the gate electrode and the source and drain electrodes; an etching stop layer between the semiconductor layer and the source and drain electrodes having a source contact hole and a drain contact hole therein; and a source buffer layer between the source electrode and the semiconductor layer and a drain buffer layer between the drain electrode and the semiconductor layer. The source and drain electrodes are metal Cu electrodes, and the source and drain buffer layers are Cu alloy layer.

    Abstract translation: 薄膜晶体管包括衬底; 栅电极，源电极，漏电极和形成在基板上的半导体层; 栅电极和半导体层之间或栅电极与源电极和漏电极之间的栅极绝缘层; 所述半导体层与所述源电极和漏电极之间的蚀刻停止层，其中具有源极接触孔和漏极接触孔; 以及源极和半导体层之间的源极缓冲层以及漏极和半导体层之间的漏极缓冲层。 源极和漏极是金属Cu电极，源极和漏极缓冲层是Cu合金层。

    Thin film transistor, array substrate and method for manufacturing the same, display device
    7.
    发明授权
    Thin film transistor, array substrate and method for manufacturing the same, display device 有权
    薄膜晶体管，阵列基板及其制造方法，显示装置

    公开(公告)号：US09209308B2

    公开(公告)日：2015-12-08

    申请号：US13985196

    申请日：2012-11-08

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Xuehui Zhang ,  Xiang Liu ,  Jainshe Xue

    IPC: H01L21/84 ,  H01L29/04 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/45 ,  H01L29/49

    CPC classification number: H01L29/78678 ,  G02F2001/134372 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66765 ,  H01L29/78693

    Abstract: There is provided a thin film transistor, comprising a substrate (1) and a gate layer (3), a gate insulating layer (4), an active layer (5), an electrode metal layer (8) and a passivation layer (9) which are formed on the substrate (1) in sequence; the electrode metal layer (8) comprises a source electrode (8a) and a drain electrode (8b), which are separated from each other with a channel region being defined therebetween; between the gate layer (3) and the substrate (1), there is formed a first transparent conductive layer (2); between the active layer (5) and the electrode metal layer (8), there is formed a second transparent conductive layer (7). The transparent conductive layers (2, 7) are added so that adhesive force between the gate metal layer (3) and the substrate (1) is enhanced, diffusion of the electrode metal to the active layer (5) is prevented.

    Abstract translation: 提供一种薄膜晶体管，其包括基板（1）和栅极层（3），栅极绝缘层（4），有源层（5），电极金属层（8）和钝化层（9） ），其顺序形成在基板（1）上; 所述电极金属层（8）包括源电极（8a）和漏电极（8b），所述源极电极（8a）和漏极电极（8b）彼此分离，沟道区域被限定在其间; 在栅极层（3）和基板（1）之间形成有第一透明导电层（2）; 在活性层（5）和电极金属层（8）之间形成有第二透明导电层（7）。 添加透明导电层（2,7），使得栅极金属层（3）和基板（1）之间的粘合力增强，从而防止了电极金属向有源层（5）的扩散。

    Thin Film Transistor and Manufacturing Method Thereof, an Array Substrate and a Display Device
    8.
    发明申请
    Thin Film Transistor and Manufacturing Method Thereof, an Array Substrate and a Display Device 有权
    薄膜晶体管及其制造方法，阵列基板和显示装置

    公开(公告)号：US20140110716A1

    公开(公告)日：2014-04-24

    申请号：US14057728

    申请日：2013-10-18

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Xiang Liu ,  Gang Wang

    IPC: H01L29/786 ,  H01L21/28 ,  H01L29/66

    CPC classification number: H01L29/786 ,  H01L21/28008 ,  H01L27/124 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7869

    Abstract: Embodiments of the present invention provide a thin film transistor and its manufacturing method, an array substrate and a display device, to improve the electrical performance of the thin film transistor and improve the picture quality of images displayed by the display device. The thin film transistor includes: a substrate; a gate, a source, a drain and a semiconductor layer formed on the substrate; a first gate protection layer; a gate isolation layer; and a second gate protection layer. The first gate protection layer is at least partly located between the gate and the semiconductor layer, and is an insulating layer. The gate isolation layer is at least partly located between the first gate protection layer and the second gate protection layer, and is a conductive layer. The second gate protection layer is at least partly located between the gate isolation layer and the semiconductor layer, and is an insulating layer.

    Abstract translation: 本发明的实施例提供薄膜晶体管及其制造方法，阵列基板和显示装置，以改善薄膜晶体管的电性能并提高由显示装置显示的图像的图像质量。 薄膜晶体管包括：基板; 形成在基板上的栅极，源极，漏极和半导体层; 第一栅极保护层; 栅极隔离层; 和第二栅极保护层。 第一栅极保护层至少部分地位于栅极和半导体层之间，并且是绝缘层。 栅极隔离层至少部分地位于第一栅极保护层和第二栅极保护层之间，并且是导电层。 第二栅极保护层至少部分地位于栅极隔离层和半导体层之间，并且是绝缘层。

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