公开(公告)号：US11967366B2

公开(公告)日：2024-04-23

申请号：US17870684

申请日：2022-07-21

申请人： NUMEM Inc.

发明人： Bindiganavale S. Nataraj

IPC分类号： G11C11/41 ,  G06N3/04 ,  G06N3/063 ,  G11C11/418 ,  G11C11/419 ,  H03K19/20 ,  H03K19/21

CPC分类号： G11C11/419 ,  G06N3/04 ,  G06N3/063 ,  G11C11/418 ,  H03K19/20 ,  H03K19/21

摘要： A memory includes an array with rows and columns of memory cells. The rows include a first row and a second row. The memory also includes a plurality of logic gates in the array. Each logic gate of the plurality of logic gates includes a first input coupled to a respective memory cell in the first row, a second input coupled to a respective memory cell in the second row, and an output. The memory further includes a plurality of sense lines in the array. The output of each logic gate of the plurality of logic gates is coupled to a sense line of the plurality of sense lines.

公开(公告)号：US11941633B2

公开(公告)日：2024-03-26

申请号：US17082664

申请日：2020-10-28

申请人： U.S. Bancorp, National Association

发明人： Christopher Kallas ,  Xiaoqiao Wei

IPC分类号： G06Q20/40 ,  G11C11/41

CPC分类号： G06Q20/4016 ,  G06Q20/4015 ,  G11C11/41

摘要： The disclosure describes an apparatus having programmed instructions that when executed cause the apparatus to receive, via a communication network, information regarding suspicious fraud activity at a first location involving a plurality of transaction cards; monitor changes over a first time interval to received information regarding suspicious fraud activity at the first location; and identify a point-of-compromise (POC) location based on monitored changes surpassing a threshold indicating suspicious fraud activity at the first location over the first time interval.

公开(公告)号：US11704549B2

公开(公告)日：2023-07-18

申请号：US17576103

申请日：2022-01-14

申请人： BrainChip, Inc.

发明人： Peter Aj Van Der Made ,  Anil S. Mankar ,  Kristofor D. Carlson ,  Marco Cheng

IPC分类号： G06N3/063 ,  G11C11/41 ,  G11C11/54 ,  G06N3/08 ,  G06N3/049 ,  G06T3/40

CPC分类号： G06N3/063 ,  G06N3/049 ,  G06N3/08 ,  G06T3/4046 ,  G11C11/41 ,  G11C11/54

摘要： Embodiments of the present invention provides a system and method of learning and classifying features to identify objects in images using a temporally coded deep spiking neural network, a classifying method by using a reconfigurable spiking neural network device or software comprising configuration logic, a plurality of reconfigurable spiking neurons and a second plurality of synapses. The spiking neural network device or software further comprises a plurality of user-selectable convolution and pooling engines. Each fully connected and convolution engine is capable of learning features, thus producing a plurality of feature map layers corresponding to a plurality of regions respectively, each of the convolution engines being used for obtaining a response of a neuron in the corresponding region. The neurons are modeled as Integrate and Fire neurons with a non-linear time constant, forming individual integrating threshold units with a spike output, eliminating the need for multiplication and addition of floating-point numbers.

公开(公告)号：US11665877B1

公开(公告)日：2023-05-30

申请号：US17564902

申请日：2021-12-29

申请人： International Business Machines Corporation

发明人： Chen Zhang ,  Ruilong Xie ,  Junli Wang ,  Dechao Guo

IPC分类号： H10B10/00 ,  G11C11/412 ,  G11C11/417 ,  G11C11/41

CPC分类号： H10B10/12 ,  G11C11/41 ,  G11C11/412 ,  G11C11/417

摘要： A compact SRAM design in a stacked architecture is provided. Notably, a 6-transistor SRAM bite cell including a bottom device level containing bottom field effect transistors and a top device level, stacked above the bottom device level, containing top field effect transistors of a different conductivity type than the bottom field effect transistors is provided.

公开(公告)号：US11631447B2

公开(公告)日：2023-04-18

申请号：US16522451

申请日：2019-07-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL YANG MING CHIAO TUNG UNIVERSITY

发明人： Wei-Xiang You ,  Pin Su ,  Kai-Shin Li ,  Chenming Hu

IPC分类号： G11C11/405 ,  G11C11/22 ,  G11C11/41 ,  H01L27/092 ,  H01L23/528 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  G11C11/24

摘要： A memory circuit includes a memory cell and a source line transistor. The memory cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second transistor and the third transistor form an inverter electrically connected to a drain of the first transistor. The inverter is configured to store two states with different applied voltages. The fourth transistor is electrically connected to a node of the inverter. The source line transistor is electrically connected to the fourth transistor.

公开(公告)号：US11563014B2

公开(公告)日：2023-01-24

申请号：US17222740

申请日：2021-04-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Hsun Chiu ,  Yih Wang

IPC分类号： H01L27/11 ,  G11C11/41 ,  H01L29/08 ,  H01L29/06 ,  G11C11/412

摘要： A memory cell is disclosed. The memory cell includes a first transistor. The first transistor includes a first conduction channel collectively constituted by one or more first nanostructures spaced apart from one another along a vertical direction. The memory cell includes a second transistor electrically coupled to the first transistor in series. The second transistor includes a second conduction channel collectively constituted by one or more second nanostructures spaced apart from one another along the vertical direction. At least one of the one or more first nanostructures is applied with first stress by a first metal structure extending, along the vertical direction, into a first drain/source region of the first transistor.

公开(公告)号：US11562706B2

公开(公告)日：2023-01-24

申请号：US17526506

申请日：2021-11-15

申请人： Japan Display Inc.

发明人： Takehiro Shima

IPC分类号： G09G3/20 ,  G09G3/36 ,  G02F1/1345 ,  G02F1/1362 ,  G11C11/41

摘要： According to one embodiment, a display device includes a pair of substrates including a display area in which pixels are arranged, pixel electrodes and memories provided in the pixels, signal lines supplied with digital signals, switching elements connecting the memories and the signal lines, scanning lines supplied with scanning signals, a first driver unit, and a second driver unit. The first driver unit is provided in a peripheral area around the display area, and supplies the digital signal to the signal line. The second driver unit is provided in the peripheral area, and supplies the scanning signal to the scanning line. In the display device, at least a part of the first driver unit is provided between the display area and the second driver unit.

公开(公告)号：US20220366959A1

公开(公告)日：2022-11-17

申请号：US17873993

申请日：2022-07-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL YANG MING CHIAO TUNG UNIVERSITY

发明人： Wei-Xiang YOU ,  Pin SU ,  Kai-Shin LI ,  Chenming HU

IPC分类号： G11C11/405 ,  H01L27/092 ,  H01L23/528 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  G11C11/22 ,  G11C11/41 ,  G11C11/24

摘要： A method includes forming a first transistor, a second transistor, a third transistor, and a fourth transistor over a substrate, wherein at least the second and third transistors include ferroelectric materials; forming an interlayer dielectric (ILD) layer over the first to fourth transistors; forming a first metal line over the ILD layer to interconnect drains of the second and third transistors and a gate of the fourth transistor; forming a second metal line over the ILD layer to interconnect a drain of the first transistor and gates of the second and third transistors; forming a write word line over the ILD layer and electrically connected to a gate of the first transistor but electrically isolated from the fourth transistor; forming a word line over the ILD layer and electrically connected to a source of the first transistor; and forming a bit line electrically connected to the fourth transistor.

公开(公告)号：US11410721B2

公开(公告)日：2022-08-09

申请号：US17199650

申请日：2021-03-12

申请人： Kioxia Corporation

发明人： Atsushi Kawasumi

IPC分类号： G11C11/41 ,  G11C11/419 ,  H01L27/11 ,  G11C11/412

摘要： A semiconductor memory device of an embodiment includes: a first inverter including a first P-channel and first N-channel transistors; a second inverter including a second P-channel and second N-channel transistors and being cross-connected to the first inverter; a third P-channel transistor; a third N-channel transistor; a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; a sixth wiring; and a controller that drives the first to sixth wirings. When writing second-level data that is at a higher potential level than first-level data into the drain of the second P-channel transistor and the drain of the second N-channel transistor, the controller puts one of the fifth wiring and the sixth wiring into a floating state.

公开(公告)号：US11379714B2

公开(公告)日：2022-07-05

申请号：US16425244

申请日：2019-05-29

申请人： British Cayman Islands Intelligo Technology Inc.

发明人： Chi-Wei Peng ,  Wei-Hsiang Tseng ,  Hong-Ching Chen ,  Shen-Jui Huang ,  Meng-Hsun Wen ,  Yu-Pao Tsai ,  Hsuan-Yi Hou ,  Ching-Hao Yu ,  Tsung-Liang Chen

IPC分类号： G06N3/06 ,  G11C11/41 ,  G06N3/063 ,  G11C11/413 ,  H03M1/82

摘要： An in-memory computing memory device is disclosed. The memory device comprises an array of memory cells, a plurality of word lines, a plurality of bit lines, (M+1) input circuits, a wordline driver and an evaluation circuitry. The array is divided into (M+1) lanes and each lane comprises P memory cell columns and an input circuit. The input circuit in each lane charges a predefined bit line with a default amount of charge proportional to an input synapse value and then distributes the default amount of charge to the other second bit lines with a predefined ratio based on a constant current. The evaluation circuitry couples a selected number of the bit lines to an accumulate line and convert an average voltage at the accumulate line into a digital value in response to a set of (M+1) input synapse values and the activated word line.