公开(公告)号：US20250041514A1

公开(公告)日：2025-02-06

申请号：US18926952

申请日：2024-10-25

Applicant: DEKA Products Limited Partnership

Inventor： Geoffrey P. Spencer ,  Robert J. Bryant

IPC: A61M5/145 ,  A61M5/142 ,  A61M5/168 ,  G06F30/34 ,  G06F115/10 ,  G16H20/17

Abstract: An infusion pump assembly includes a reservoir assembly configured to contain an infusible fluid. A motor assembly is configured to act upon the reservoir assembly and dispense at least a portion of the infusible fluid contained within the reservoir assembly. Processing logic is configured to control the motor assembly. The processing logic includes a primary microprocessor configured to execute one or more primary applications written in a first computer language; and a safety microprocessor configured to execute one or more safety applications written in a second computer language.

公开(公告)号：US20240422898A1

公开(公告)日：2024-12-19

申请号：US18815694

申请日：2024-08-26

Applicant: Albert Moses Haim

Inventor： Albert Moses Haim

IPC: H05K1/02 ,  G06F30/34 ,  G06F30/347 ,  G06F30/392 ,  H05K1/11

Abstract: A dynamically reconfigurable circuit, and method, includes a magnetically responsive material configured to alter an electrical conductivity thereof in response to an external magnetic field; a magnet operatively positioned to influence the magnetically responsive material, wherein the magnet is configured to create or modify circuit pathways by selectively aligning particles within the magnetically responsive material; and tuning elements including tuning screws and tuning contacts configured to adjust an alignment and density of the magnetically responsive material to adjust conductivity and reconfiguration of the circuit pathways.

公开(公告)号：US12153865B2

公开(公告)日：2024-11-26

申请号：US18195324

申请日：2023-05-09

Applicant: iCometrue Company Ltd.

Inventor： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC: G06F30/34 ,  G05B19/042 ,  G06F3/06 ,  G11C7/10 ,  G11C11/412 ,  H01L25/16 ,  H01L25/18 ,  H03K19/177 ,  H03K19/1776 ,  H10B20/00 ,  H10B41/35

Abstract: A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

公开(公告)号：US12073308B2

公开(公告)日：2024-08-27

申请号：US15423279

申请日：2017-02-02

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Thomas Boesch ,  Giuseppe Desoli

IPC: G06N3/063 ,  G06F30/327 ,  G06F30/34 ,  G06F30/347 ,  G06N3/044 ,  G06N3/045 ,  G06N3/0464 ,  G06N3/047 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06F9/445 ,  G06F13/40 ,  G06F15/78 ,  G06F115/02 ,  G06F115/08 ,  G06N3/04 ,  G06N3/08 ,  G06N7/01

CPC classification number: G06N3/0464 ,  G06F30/327 ,  G06F30/34 ,  G06F30/347 ,  G06N3/044 ,  G06N3/045 ,  G06N3/047 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06F9/44505 ,  G06F13/4022 ,  G06F15/7817 ,  G06F2115/02 ,  G06F2115/08 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N7/01

Abstract: Embodiments are directed towards a hardware accelerator engine that supports efficient mapping of convolutional stages of deep neural network algorithms. The hardware accelerator engine includes a plurality of convolution accelerators, and each one of the plurality of convolution accelerators includes a kernel buffer, a feature line buffer, and a plurality of multiply-accumulate (MAC) units. The MAC units are arranged to multiply and accumulate data received from both the kernel buffer and the feature line buffer. The hardware accelerator engine also includes at least one input bus coupled to an output bus port of a stream switch, at least one output bus coupled to an input bus port of the stream switch, or at least one input bus and at least one output bus hard wired to respective output bus and input bus ports of the stream switch.

公开(公告)号：US12008371B2

公开(公告)日：2024-06-11

申请号：US17886855

申请日：2022-08-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel

IPC: G06F9/30 ,  G06F9/48 ,  G06F30/34

CPC classification number: G06F9/30123 ,  G06F9/30043 ,  G06F9/30079 ,  G06F9/4881 ,  G06F30/34

Abstract: Systems, apparatuses, and methods for implementing as part of a processor pipeline a reprogrammable execution unit capable of executing specialized instructions are disclosed. A processor includes one or more reprogrammable execution units which can be programmed to execute different types of customized instructions. When the processor loads a program for execution, the processor loads a bitfile associated with the program. The processor programs a reprogrammable execution unit with the bitfile so that the reprogrammable execution unit is capable of executing specialized instructions associated with the program. During execution, a dispatch unit dispatches the specialized instructions to the reprogrammable execution unit for execution. The results of other instructions, such as integer and floating point instructions, are available immediately to instructions executing on the reprogrammable execution unit since the reprogrammable execution unit shares the processor registers with the integer and floating point execution units.

公开(公告)号：US20240112460A1

公开(公告)日：2024-04-04

申请号：US18478335

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Narayan Srinivasa

IPC: G06V20/00 ,  G06F18/214 ,  G06F30/34 ,  G06N3/08 ,  G06V10/44 ,  G06V10/764 ,  G06V10/774 ,  G09G3/20 ,  G09G3/36

CPC classification number: G06V20/00 ,  G06F18/214 ,  G06F30/34 ,  G06N3/08 ,  G06V10/454 ,  G06V10/764 ,  G06V10/774 ,  G09G3/2003 ,  G09G3/3607

Abstract: Apparatuses, methods, and articles of manufacture are disclosed. An example apparatus includes processor circuitry to assign a location value hyperdimensional vector (HDV) to a location in an image of a first patch of one or more pixels, assign at least a first channel HDV to the first patch, determine at least one pixel intensity value HDV for each of the one or more pixels in the first patch, bind together each of the pixel intensity value HDVs into at least one patch intensity value HDV, bind together the at least first channel HDV and the at least one patch intensity value HDV to produce a patch consensus intensity HDV, and generate a first hyperdimensional representation patch value HDV of the first patch by binding together at least a combination of the patch consensus intensity HDV and the location value HDV.

公开(公告)号：US11853668B1

公开(公告)日：2023-12-26

申请号：US16579502

申请日：2019-09-23

Applicant: Synopsys, Inc.

Inventor： Ngai Ngai William Hung ,  Dhiraj Goswami

IPC: G06F30/34 ,  G06F11/26 ,  G06F21/76 ,  G06F11/36

CPC classification number: G06F30/34 ,  G06F11/261 ,  G06F11/3652 ,  G06F21/76

Abstract: A system and a method are disclosed for emulating a design of an electronic circuit. One or more field programmable gate array (FPGA) overlays are programmed to implement a first set of logic elements of the design of the electronic circuit. A second set of logic elements of the design of the electronic circuit is implemented in one or more FPGAs. The FPGA overlays implementing the first set of logic elements and the FPGAs implementing the second set of logic elements are interconnected to each other. The design of the electronic circuit is then tested using the interconnected FPGA overlays and the FPGAs.

公开(公告)号：US11836460B2

公开(公告)日：2023-12-05

申请号：US17171174

申请日：2021-02-09

Applicant: Imagination Technologies Limited

Inventor： Theo Alan Drane

IPC: G06F7/535 ,  G06F30/327 ,  G06F30/34 ,  G06F7/523 ,  G06F7/38

CPC classification number: G06F7/523 ,  G06F7/38 ,  G06F7/535 ,  G06F30/327 ,  G06F30/34 ,  G06F2207/5356

Abstract: A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite number of the repeating sections whilst still satisfying a defined error bound. To further reduce the size of the summation array, the binary representation of the invariant rational is converted into canonical signed digit notation prior to creating the finite representation of the infinite array.

公开(公告)号：US11831486B2

公开(公告)日：2023-11-28

申请号：US17702707

申请日：2022-03-23

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar

IPC: H04L41/046 ,  G06F15/78 ,  H04L41/0896 ,  H04L9/08 ,  G06F30/34 ,  G06F13/42 ,  G06F21/76

CPC classification number: H04L41/046 ,  G06F15/7889 ,  G06F30/34 ,  H04L9/0894 ,  H04L41/0896 ,  G06F13/4221 ,  G06F21/76 ,  H04L2209/122

Abstract: Mechanisms for out-of-band (OOB) management of Field Programmable Gate Array (FPGA) bitstreams and associated methods, apparatus, systems and firmware. Under a first OOB mechanism, a management component, such as a baseband management controller (BMC) is coupled to a processor including an agent in a compute node that includes an FGPA. An FPGA bitstream file is provided to the BMC, and the agent reads the file from the BMC and streams the FPGA bitstream contents in the file to the FPGA to program it. Under second and third OOB mechanisms, a pointer to an FPGA bitstream file that identifies the location of the file that is accessible via a network or fabric is provided to the BMC or other management entity. The BMC/management entity forwards the pointer to BIOS running on the compute node or an agent on the processor. The BIOS or agent then uses the pointer to retrieve the FPGA bitstream file via the network or fabric, as applicable, and streams the FPGA bitstream to the FPGA to program it.

公开(公告)号：US11829695B2

公开(公告)日：2023-11-28

申请号：US17402632

申请日：2021-08-16

Applicant: S2C Limited

Inventor： Jifeng Zhang ,  Chuan Li

IPC: G06F30/34 ,  G06F30/392 ,  G06F30/3312 ,  G06F30/327

CPC classification number: G06F30/34 ,  G06F30/327 ,  G06F30/3312 ,  G06F30/392

Abstract: A method for logic design partitioning includes: collecting an RTL design file used for describing a logic circuit; performing syntax analysis processing on the RTL design file; extracting an always object and an assign object from logic model objects, and encapsulating the always object and the assign object, respectively; constructing and generating a hypergraph-based data structure; performing attribute analysis, and obtaining operating frequency information by processing according to clock domain information; associating and storing the clock domain information and the operating frequency information with corresponding nodes; and performing partitioning processing to obtain corresponding partitioned data. By means of the solutions of the present invention, other processing at the back end of the flow is not affected, the partitioning time is reduced and the partitioning efficiency is improved. Meanwhile, the logic content in chip design is partitioned efficiently, reasonably and correctly.