公开(公告)号：US09958917B1

公开(公告)日：2018-05-01

申请号：US15368457

申请日：2016-12-02

Applicant: Synopsys, Inc.

Inventor： Ngai Ngai William Hung ,  Dhiraj Goswami

IPC: G11C7/10 ,  G06F1/24 ,  G11C7/22 ,  G06F13/10 ,  G06F13/12 ,  G06F11/30

CPC classification number: G06F1/24 ,  G06F11/3037 ,  G06F11/3055 ,  G06F13/105 ,  G06F13/124 ,  G11C7/20 ,  G11C29/16 ,  G11C29/46 ,  G11C29/50012

Abstract: Disclosed is a resettable memory device including a memory unit, a reset status indicator circuit, a logic sampling circuit, and a multiplexer for performing a reset function. The memory unit includes cells for storing states of signals in a design under test. The reset status indicator stores states of indicators indicating whether corresponding cells should be reset or not. Responsive to the reset status indicator indicating that the value of the cell should not be reset, the multiplexer receives the value stored in the cell and outputs the retrieved value from the cell. Responsive to the reset status indicator indicating that the value of the cell should be reset, the multiplexer outputs a reset value instead of the value stored in the cell. The reset value may be changed by the logic sampling circuit at different time periods or certain logic conditions, and output through the multiplexer.

公开(公告)号：US20160034624A1

公开(公告)日：2016-02-04

申请号：US14881029

申请日：2015-10-12

Applicant: Synopsys, Inc.

Inventor： Ngai Ngai William Hung ,  Qiang Qiang ,  Guillermo R. Maturana ,  Jasvinder Singh ,  Dhiraj Goswami

IPC: G06F17/50 ,  G06F7/58

CPC classification number: G06F17/5045 ,  G06F7/582 ,  G06F17/11 ,  G06F2217/06

Abstract: Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking when the system attempts to assign random values to the set of random variables in a manner that satisfies the set of constraints. The system can rewrite the set of constraints to obtain a new set of constraints that is expected to reduce and/or avoid the performance problems. The system can then assign random values to the set of random variables based on the new set of constraints.

Abstract translation: 描述用于将随机值分配给一组随机变量的方法和装置，使得分配的随机值满足一组约束。 约束求解器可以接收一组约束，当系统以满足约束集合的方式将随机值分配给随机变量集合时，预期会导致性能问题。 例如，当系统尝试以满足约束集合的方式将随机值分配给随机变量集时，模约束和位片约束可导致系统执行过多的回溯。 系统可以重写一组约束以获得预期会减少和/或避免性能问题的新的一组约束。 然后，系统可以基于新的约束集将随机值分配给随机变量集合。

公开(公告)号：US09202005B2

公开(公告)日：2015-12-01

申请号：US14472058

申请日：2014-08-28

Applicant: Synopsys, Inc.

Inventor： Dhiraj Goswami ,  Aijun Hu ,  Na Xing ,  Jason Chung-Shih Chen ,  Ngai Ngai William Hung

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009

Abstract: A design verification workstation contains both debug and constraint solver capabilities during simulation of a design under test. The design verification workstation is configured to allow the user to debug constraints, stop the constraint solver, navigate problems and variables, and make modifications on-the fly during the simulation to constraint information. Additionally, in some embodiments, the design verification workstation may allow a user to use a constraint solver to experiment if the modifications will lead to desired test stimulus. Since this debug process happens during simulation, users do not need to recompile the test case. Additionally, once a user is satisfied with the modifications made to the simulation, the modification could be saved for future usage.

Abstract translation: 设计验证工作站在模拟被测设计期间包含调试和约束求解器功能。 设计验证工作站被配置为允许用户调试约束，停止约束求解器，导航问题和变量，并在仿真期间对约束信息进行修改。 另外，在一些实施例中，设计验证工作站可以允许用户使用约束求解器来实验，如果修改将导致期望的测试刺激。 由于调试过程在模拟过程中发生，用户无需重新编译测试用例。 另外，一旦用户对对模拟进行的修改满意，则可以节省修改以供将来使用。

公开(公告)号：US11853668B1

公开(公告)日：2023-12-26

申请号：US16579502

申请日：2019-09-23

Applicant: Synopsys, Inc.

Inventor： Ngai Ngai William Hung ,  Dhiraj Goswami

IPC: G06F30/34 ,  G06F11/26 ,  G06F21/76 ,  G06F11/36

CPC classification number: G06F30/34 ,  G06F11/261 ,  G06F11/3652 ,  G06F21/76

Abstract: A system and a method are disclosed for emulating a design of an electronic circuit. One or more field programmable gate array (FPGA) overlays are programmed to implement a first set of logic elements of the design of the electronic circuit. A second set of logic elements of the design of the electronic circuit is implemented in one or more FPGAs. The FPGA overlays implementing the first set of logic elements and the FPGAs implementing the second set of logic elements are interconnected to each other. The design of the electronic circuit is then tested using the interconnected FPGA overlays and the FPGAs.

公开(公告)号：US11468218B2

公开(公告)日：2022-10-11

申请号：US13766749

申请日：2013-02-13

Applicant: Synopsys, Inc.

Inventor： Dhiraj Goswami ,  Ngai Ngai William Hung

IPC: G06F30/30 ,  G06F30/33 ,  G06F30/3323

Abstract: Computer-implemented techniques are disclosed for verifying circuit designs using subgraph caching. A device under test (DUT) is modeled as a graph. The graph is partitioned into one or more subgraphs and problems are generated for each subgraph. Graph and subgraph problem generation is repeated numerous times throughout the verification process. Problems and sub-problems are generated and solved. When a subgraph problem is solved, the problem's variables, values, and information can be stored in a cache. The storage can be based on entropy of variables used in the graph and subgraph problems. The subgraph problem storage cache can be searched for previously stored problems which match another problem in need of a solution. By retrieving subproblem variables, values, and information from the cache, the computational overhead of circuit design verification is reduced as problems are reused. Caching can be accomplished using an information theoretic approach.

公开(公告)号：US10372856B2

公开(公告)日：2019-08-06

申请号：US14881029

申请日：2015-10-12

Applicant: Synopsys, Inc.

Inventor： Ngai Ngai William Hung ,  Qiang Qiang ,  Guillermo R. Maturana ,  Jasvinder Singh ,  Dhiraj Goswami

IPC: G06F17/50 ,  G06F17/11 ,  G06F7/58

Abstract: Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking when the system attempts to assign random values to the set of random variables in a manner that satisfies the set of constraints. The system can rewrite the set of constraints to obtain a new set of constraints that is expected to reduce and/or avoid the performance problems. The system can then assign random values to the set of random variables based on the new set of constraints.

公开(公告)号：US20150067622A1

公开(公告)日：2015-03-05

申请号：US14472058

申请日：2014-08-28

Applicant: Synopsys, Inc.

Inventor： Dhiraj Goswami ,  Aijun Hu ,  Na Xing ,  Jason Chung-Shih Chen ,  Ngai Ngai William Hung

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009

Abstract: A design verification workstation contains both debug and constraint solver capabilities during simulation of a design under test. The design verification workstation is configured to allow the user to debug constraints, stop the constraint solver, navigate problems and variables, and make modifications on-the fly during the simulation to constraint information. Additionally, in some embodiments, the design verification workstation may allow a user to use a constraint solver to experiment if the modifications will lead to desired test stimulus. Since this debug process happens during simulation, users do not need to recompile the test case. Additionally, once a user is satisfied with the modifications made to the simulation, the modification could be saved for future usage.

Abstract translation: 设计验证工作站在模拟被测设计期间包含调试和约束求解器功能。 设计验证工作站被配置为允许用户调试约束，停止约束求解器，导航问题和变量，并在仿真期间对约束信息进行修改。 另外，在一些实施例中，设计验证工作站可以允许用户使用约束求解器来实验，如果修改将导致期望的测试刺激。 由于调试过程在模拟过程中发生，用户无需重新编译测试用例。 另外，一旦用户对对模拟进行的修改满意，则可以节省修改以供将来使用。

公开(公告)号：US10325046B2

公开(公告)日：2019-06-18

申请号：US15705784

申请日：2017-09-15

Applicant: Synopsys, Inc.

Inventor： Lingyi Liu ,  Ngai Ngai William Hung ,  Sitanshu Seth ,  Leonid Alexander Broukhis ,  Dhiraj Goswami

IPC: G06F9/455 ,  G06F17/50

Abstract: Configuring a hardware verification system includes receiving first data representing a first integrated circuit design configured to operate via a first clock signal derived from a second clock signal and a third signal generated by the second clock signal. The computer transforms the first data into second data representing a second design that includes functionality of the first design. The transformation replaces the first clock signal with the second clock signal. A first Boolean function is defined by first and second values of the third signal corresponding to a first transition of the second clock signal being in a same direction as a transition of the first clock signal. A second Boolean function is defined by the first and second values of the third signal corresponding to a second transition of the second clock signal being in a direction opposite to the associated transition of the first clock signal.

公开(公告)号：US20180082004A1

公开(公告)日：2018-03-22

申请号：US15705784

申请日：2017-09-15

Applicant: Synopsys, Inc.

Inventor： Lingyi Liu ,  Ngai Ngai William Hung ,  Sitanshu Seth ,  Leonid Alexander Broukhis ,  Dhiraj Goswami

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5027 ,  G06F17/504 ,  G06F17/5054 ,  G06F2217/62

Abstract: Configuring a hardware verification system includes receiving first data representing a first integrated circuit design configured to operate via a first clock signal derived from a second clock signal and a third signal generated by the second clock signal. The computer transforms the first data into second data representing a second design that includes functionality of the first design. The transformation replaces the first clock signal with the second clock signal. A first Boolean function is defined by first and second values of the third signal corresponding to a first transition of the second clock signal being in a same direction as a transition of the first clock signal. A second Boolean function is defined by the first and second values of the third signal corresponding to a second transition of the second clock signal being in a direction opposite to the associated transition of the first clock signal.

公开(公告)号：US20140068533A1

公开(公告)日：2014-03-06

申请号：US13766749

申请日：2013-02-13

Applicant: SYNOPSYS, INC.

Inventor： Dhiraj Goswami ,  Ngai Ngai William Hung

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5022 ,  G06F17/504

Abstract: Computer-implemented techniques are disclosed for verifying circuit designs using subgraph caching. A device under test (DUT) is modeled as a graph. The graph is partitioned into one or more subgraphs and problems are generated for each subgraph. Graph and subgraph problem generation is repeated numerous times throughout the verification process. Problems and sub-problems are generated and solved. When a subgraph problem is solved, the problem's variables, values, and information can be stored in a cache. The storage can be based on entropy of variables used in the graph and subgraph problems. The subgraph problem storage cache can be searched for previously stored problems which match another problem in need of a solution. By retrieving subproblem variables, values, and information from the cache, the computational overhead of circuit design verification is reduced as problems are reused. Caching can be accomplished using an information theoretic approach.

Abstract translation: 公开了使用子图缓存来验证电路设计的计算机实现的技术。 被测设备（DUT）被建模为图形。 图形被划分成一个或多个子图，并为每个子图生成问题。 图形和子图问题的产生在整个验证过程中重复了很多次。 产生和解决问题和子问题。 当解决子图问题时，问题的变量，值和信息可以存储在缓存中。 存储可以基于图中使用的变量的熵和子图问题。 子图问题存储缓存可以搜索与需要解决方案的另一个问题相匹配的先前存储的问题。 通过从缓存中检索子问题变量，值和信息，减少了电路设计验证的计算开销，因为问题被重用。 可以使用信息理论方法来实现缓存。