公开(公告)号：US20240311538A1

公开(公告)日：2024-09-19

申请号：US18121143

申请日：2023-03-14

申请人： Cadence Design Systems, Inc.

发明人： Matheus Nogueira Fonseca ,  Lars Lundgren ,  Gabriel Guedes de Azevedo Barbosa ,  Paula Selegato Mathias ,  Luis Humberto Rezende Barbosa ,  Bárbara Leite Almeida ,  Thamara Karen Cunha Andrade ,  Gustavo Augusto Silva Junqueira ,  João Paulo Magalhães de Melo dos Santos

IPC分类号： G06F30/327 ,  G06F11/36 ,  G06F30/331

CPC分类号： G06F30/327 ,  G06F11/3652 ,  G06F30/331 ,  G06F2119/12

摘要： Embodiments include herein are directed towards a system and method for glitch debugging in an electronic design. Embodiments may include receiving, using a processor, the electronic design and performing a formal glitch analysis of the electronic design to determine if one or more glitches are present in a clock logic of the electronic design. If a glitch is identified, embodiments may further include causing a generation of a graphical glitch debugger display. Embodiments may include receiving an edit to the electronic design and re-performing the formal glitch analysis of the electronic design to determine whether a glitch is present.

公开(公告)号：US11829279B2

公开(公告)日：2023-11-28

申请号：US17483521

申请日：2021-09-23

申请人： Intel Corporation

发明人： Martin-Thomas Grymel ,  David Bernard ,  Martin Power ,  Niall Hanrahan ,  Kevin Brady

IPC分类号： G06F11/00 ,  G06F11/36 ,  G06N3/04 ,  G06F11/277 ,  G06F11/30

CPC分类号： G06F11/3652 ,  G06F11/277 ,  G06F11/3075 ,  G06F11/3656 ,  G06N3/04

摘要： Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.

公开(公告)号：US20180349252A1

公开(公告)日：2018-12-06

申请号：US15615398

申请日：2017-06-06

申请人： Microsoft Technology Licensing, LLC

发明人： Aaron RODRIGUEZ HERNANDEZ ,  Jason GOULD ,  Cole BROOKING ,  Nihar MOHAPATRA ,  Parikshit NARKHEDE ,  Veena K. MALWANKAR

IPC分类号： G06F11/36 ,  G06F11/34 ,  G06F17/30

CPC分类号： G06F11/3652 ,  G06F11/261 ,  G06F11/3457 ,  G06F16/50

摘要： Methods and devices for testing graphics hardware may include reading content of a selected capture file from a plurality of capture files. The methods and devices may include transferring content from the selected capture file to an emulator memory of an emulator separate from the computer device. The methods and devices may include executing at least one pseudo central processing unit (pseudo CPU) operation to coordinate the execution of work on a graphics processing unit (GPU) of the emulator using the content from the selected capture file to test the GPU. The methods and devices may include receiving and store rendered image content from the emulator when the work is completed.

公开(公告)号：US20180074940A1

公开(公告)日：2018-03-15

申请号：US15701047

申请日：2017-09-11

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Mamoru YAMAMOTO ,  Shinsuke FUKUSHIMA

IPC分类号： G06F11/36

CPC分类号： G06F11/3656 ,  G06F11/3652

摘要： A microcomputer includes a CPU core, a memory which stores a program to be debugged and a debugging program, an event detection unit which detects establishment of an event, a debug interruption generation unit which transits a program to the debugging program when the event is established, and a debug interface control unit. The CPU core executes the debugging program, thereby informing an emulator of an event number of the established event through the debug interface control unit, and right thereafter restarting execution of the program to be debugged.

公开(公告)号：US09852244B2

公开(公告)日：2017-12-26

申请号：US15007040

申请日：2016-01-26

申请人： Synopsys, Inc.

发明人： Ludovic Marc Larzul ,  Alexander Rabinovitch

IPC分类号： G06F17/50 ,  G06F11/36

CPC分类号： G06F17/5027 ,  G06F11/3636 ,  G06F11/3652 ,  G06F17/5022 ,  G06F17/5045 ,  G06F17/5054

摘要： An emulation environment includes a host system and an emulator. The host system configures the emulator to emulate a design under test (DUT) and the emulator emulates the DUT accordingly. During emulation, the emulator traces limited signals of the DUT and stores values of the traced signals. When values of certain signals of the DUT are needed for analysis or verification of the DUT but the signals were not traced by the emulator, the host system simulates one or more sections of the DUT to obtain values of the signals. Signals traced by the emulator are used as inputs to simulate the one or more sections.

公开(公告)号：US09759770B2

公开(公告)日：2017-09-12

申请号：US14804500

申请日：2015-07-21

申请人： dSPACE digital signal processing and control engineering GmbH

发明人： Matthias Bockelkamp ,  Marc Dressler

IPC分类号： G06F11/00 ,  G01R31/3177 ,  G06F11/36 ,  G06F21/57

CPC分类号： G01R31/3177 ,  G06F11/3648 ,  G06F11/3652 ,  G06F11/3656 ,  G06F21/575

摘要： An arrangement for the partial release of a debug interface of a programmable hardware component, whereby a first logic for the programmable hardware component can be stored in a configuration memory and a configuration device is designed to program the programmable hardware component via a configuration interface of the programmable hardware component according to the first logic. The configuration device is further designed to register a programming process of the programmable hardware component which occurs via the debug interface according to a second logic and, upon termination of the programming process occurring via the debug interface, reprograms the programmable hardware component according to the first logic.

公开(公告)号：US09535817B2

公开(公告)日：2017-01-03

申请号：US13158345

申请日：2011-06-10

申请人： Vamsee R K Aluru ,  Pankaj Kachrulal Sarda ,  Madhu Vadlapudi

发明人： Vamsee R K Aluru ,  Pankaj Kachrulal Sarda ,  Madhu Vadlapudi

IPC分类号： G06F17/50 ,  G06F17/30 ,  G06F9/44 ,  G06F11/36

CPC分类号： G06F11/3664 ,  G06F11/3652 ,  G06F17/5022

摘要： A method for developing and testing an application for a device with one or more sensors using a sensor emulation environment that may allow testing of the application in a programmatic manner. The sensor emulation environment may emulate actual physical sensors. The sensor emulation environment may receive sensor simulation data from multiple types of sources of sensor data. A sensor data engine may receive sensor simulation data from a selected data source via an API. The data engine may provide data values at times that represent operation of a sensor. The sensor emulation environment may further include a sensor interface component that emulates a hardware interface to the emulated sensor in a physical target device such that application components, such as a driver, may interact with the sensor emulation environment.

摘要翻译： 使用可以允许以编程方式测试应用的传感器仿真环境来开发和测试具有一个或多个传感器的设备的应用的方法。 传感器仿真环境可以模拟实际物理传感器。 传感器仿真环境可以从多种类型的传感器数据源接收传感器模拟数据。 传感器数据引擎可以经由API从所选择的数据源接收传感器模拟数据。 数据引擎可以在代表传感器的操作的时候提供数据值。 传感器仿真环境还可以包括传感器接口组件，其在物理目标设备中仿真到仿真传感器的硬件接口，使得诸如驱动器的应用组件可以与传感器仿真环境交互。

公开(公告)号：US09514026B2

公开(公告)日：2016-12-06

申请号：US14858280

申请日：2015-09-18

申请人： Oracle International Corporation

发明人： John Smiljanic ,  Shailesh Vinayaka ,  James Driscoll

IPC分类号： G06F9/44 ,  G06F11/00 ,  G06F11/36 ,  G06F9/455

CPC分类号： G06F11/3612 ,  G06F9/45558 ,  G06F11/36 ,  G06F11/362 ,  G06F11/3636 ,  G06F11/3652 ,  G06F11/3664 ,  G06F2009/45591

摘要： Various arrangements for debugging logic being executed by a webserver is presented. A virtual machine of the webserver may execute runtime threads for a plurality of remote users. The web server may compile business logic code received from a developer computer system via a web-based interface into an logic insight injected code. The logic insight injected code may be compiled from the business logic code to include debugging functionality. The virtual machine of the webserver may execute the logic insight injected code concurrently with the runtime threads being executed for the plurality of remote users. The debugging functionality of the logic insight injected code being executed may not affect execution of the runtime threads for the plurality of users.

公开(公告)号：US09384107B2

公开(公告)日：2016-07-05

申请号：US13292027

申请日：2011-11-08

申请人： William E. Jacobus

发明人： William E. Jacobus

IPC分类号： G06F11/26 ,  G06F11/36 ,  G01R19/165 ,  G01R31/316 ,  G01R31/302 ,  G01R31/30 ,  G01R31/317 ,  G01R31/3167 ,  G01R19/00 ,  G01R31/28

CPC分类号： G06F11/261 ,  G01R19/0038 ,  G01R19/165 ,  G01R31/2851 ,  G01R31/30 ,  G01R31/302 ,  G01R31/316 ,  G01R31/3167 ,  G01R31/317 ,  G06F11/3652

摘要： Method and apparatus for detecting an improper voltage levels between a hardware emulator and an auxiliary hardware device are provided. In various implementations, a voltage level detector is attached to a bus that connects an emulator with an auxiliary hardware device. Subsequently, the voltage level detector can be used to detect when operating conditions on the bus are outside specification. More specifically, when the voltage level on the bus falls outside a threshold level, the voltage level detector may be used to alert a user, pause operation of the emulator or both.

摘要翻译： 提供了用于检测硬件仿真器和辅助硬件设备之间不正确的电压电平的方法和装置。 在各种实现中，将电压电平检测器连接到将仿真器与辅助硬件设备连接的总线。 随后，可以使用电压电平检测器来检测总线上的工作条件是否超出规范。 更具体地，当总线上的电压电平降到阈值以下时，电压电平检测器可以用于警告用户，暂停模拟器的操作或两者。

公开(公告)号：US09183113B2

公开(公告)日：2015-11-10

申请号：US13593098

申请日：2012-08-23

申请人： John Smiljanic ,  Shailesh Vinayaka ,  James Driscoll

发明人： John Smiljanic ,  Shailesh Vinayaka ,  James Driscoll

IPC分类号： G06F9/44 ,  G06F11/00 ,  G06F11/36

CPC分类号： G06F11/3612 ,  G06F9/45558 ,  G06F11/36 ,  G06F11/362 ,  G06F11/3636 ,  G06F11/3652 ,  G06F11/3664 ,  G06F2009/45591

摘要： Various arrangements for debugging logic being executed by a webserver is presented. A virtual machine of the webserver may execute runtime threads for a plurality of remote users. The web server may compile business logic code received from a developer computer system via a web-based interface into an logic insight injected code. The logic insight injected code may be compiled from the business logic code to include debugging functionality. The virtual machine of the webserver may execute the logic insight injected code concurrently with the runtime threads being executed for the plurality of remote users. The debugging functionality of the logic insight injected code being executed may not affect execution of the runtime threads for the plurality of users.

摘要翻译： 呈现了由网络服务器执行的用于调试逻辑的各种布置。 web服务器的虚拟机可以为多个远程用户执行运行时线程。 网络服务器可以将从开发者计算机系统接收的业务逻辑代码通过基于网络的接口编译成逻辑洞察注入代码。 逻辑洞察注入代码可以从业务逻辑代码编译成包括调试功能。 web服务器的虚拟机可以与为多个远程用户执行的运行时线程同时地执行注入注入逻辑的洞察力。 正在执行的逻辑洞察注入代码的调试功能可能不会影响多个用户的运行时线程的执行。