- 专利标题: Systems, apparatus, and methods to debug accelerator hardware
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申请号: US17483521申请日: 2021-09-23
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公开(公告)号: US11829279B2公开(公告)日: 2023-11-28
- 发明人: Martin-Thomas Grymel , David Bernard , Martin Power , Niall Hanrahan , Kevin Brady
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Akona IP PC
- 主分类号: G06F11/00
- IPC分类号: G06F11/00 ; G06F11/36 ; G06N3/04 ; G06F11/277 ; G06F11/30
摘要:
Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.
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